S1M8831A Samsung Semiconductor, Inc., S1M8831A Datasheet
S1M8831A
Related parts for S1M8831A
S1M8831A Summary of contents
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... IS-95 CDMA and IMT2000. Various program-controlled power down options as well as low supply voltage help the design of wireless cell phones having minimum power consumption. Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8831A/33 has a linear phase detector characteristic and can be used for very stable, low noise PLLs. Supply voltage can range from 2. ...
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... S1M8831A/33 APPLICATIONS High-rate data-service cellular telephones (for CDMA): S1M8831A, S1M8833 High-rate data-service portable wireless communications (for Korean-PCS): S1M8833 Other wireless communications systems ORDERING INFORMATION Device +S1M8831A01-G0T0 +S1M8833X01-G0T0 + : New Product 2 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Package Operating Temperature 24-QFN-3.5 4.5 -40 to +85C ...
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... Counter 10 11 foLD RF_EN Phase Charge Detector Pump IF Prescaler - + IF Prescaler Control Counter IF N-Latch 2-Bit Control 24-Bit Shift Register IF R-Latch IF Reference Counter 12 IF_EN S1M8831A/ DGND GND DATA 13 CLOCK 3 ...
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... S1M8831A/33 PIN CONFIGURATION DGND GND RF OSCx OSCin 4 OUT0 OUT1 S1M8831A/ foLD RF_EN 24-QFN FRACTIONAL-N RF/INTEGER-N IF DUAL PLL DGND ...
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... IF Prescaler complementary input. For a single-ended output IF VCO, a bypass capacitor should be placed as close as possible to this pin. IF prescaler input. Small signal input from the VCO. Ground for IF PLL digital circuitry. IF charge pump output. Connected to an external loop filter. S1M8831A/33 Description IF and V IF ...
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... S1M8831A/33 PIN DESCRIPTION (Continued) Pin No. Pin Name I – – OUT1 O 24 OUT0 O 6 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL Descriptions Power supply for IF charge pump. Must be IF PLL power supply (2.7V to 4.0V). Must be equal to V Programmable CMOS output. Level of the output is controlled by RF_N[19] bit ...
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... FRACTIONAL-N RF/INTEGER-N IF DUAL PLL EQUIVALENT CIRCUIT DIAGRAM CLOCK, DATA RF OSCin, OSCx f RF, f RF bias foLD S1M8831A/33 7 ...
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... S1M8831A/33 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Characteristics Power supply voltage Voltage on any pin with GND = 0 volts Power dissipation Operating temperature Storage temperature ELECTROSTATIC CHARACTERISTICS Characteristics Human body model Machine model Charge device model NOTE: These devices are ESD sensitive. These devices must be handled in an ESD protected environment. ...
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... FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ELECTRICAL CHARACTERISTICS (V = 3.0V 3.0V unless otherwise specified Characteristic Power supply voltage Power supply current S1M8831A RF+IF S1M8833 RF+IF S1M8831A RF+IF S1M8833 RF+IF IF only Power down current Digital Inputs: CLOCK, DATA and LE High level input voltage Low level input voltage High level input current ...
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... unless otherwise specified Characteristic Operating Frequency, Input Sensitivity (Programmable Divider, PFD) RF operating S1M8833 frequency S1M8831A IF operating frequency Reference oscillator input frequency Phase detector operating frequency RF input sensitivity IF input sensitivity Reference oscillator input sensitivity Charge Pump Outputs: CPoRF, CPoIF ...
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... Test Conditions I 0. CPL CP-SIINK CP-SOURCE 0. -0. CLOCK t CWH t CWL LEW t CLE S1M8831A/33 Min. Typ. Max. -2.5 +2 Unit MHz ...
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... ECL switching level to drive the following ECL divider so that it can normally operate even in a smaller input power less than -10dBm. The amplified VCO output signal is divided by the prescaler with a pre-determined divide ratio (div. 8/9 in S1M8831A, div. 16/17 in S1M8833, div. 8/9 in IF), the N counter, or the Fractional-N circuitry ( - modulator) ...
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... The RF N counter can be configured as a fractional counter. The fractional-N counter is selected when the Frac- N_SEL bit becomes HIGH. In the fractional mode, the S1M8831A is capable of offering a continuous integer divide range from 72 to 1008 and the S1M8833 offering a continuous integer divide range from 161 to 168. ...
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... The clock frequency fixed at 9.84MHz ( = 19.68MHz/2) is recommended for the - modulator which is an optimum condition for achieving better electrical performances related to the fractional noise and power consumption. Only when using the clock frequency, the S1M8831A/33 guarantees the exact frequency resolutions: 10kHz for CDMA PCS and 30kHz for CDMA cellular. ...
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... FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PROGRAMMING DESCRIPTION The S1M8831A/33 can be programmed via the serial bus interface. The interface is made of 3 functional signals: clock, data, and latch enable(LE). Serial data is moved into the 24-bit shift register on the rising edge of the clock. These data enters MSB first. When LE goes HIGH, data in the shift register is moved into one of the 4 latches (by the 2-bit control) ...
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... S1M8831A/33 Control Words Control bits OSC IF_N[22] IF_CTL_WORD IF_N[21] IF_N[20] IF_N[19] IF_CP_WORD IF_N[18] IF_N[17] RF_CTL_WORD RF_N[23] RF_N[22] RF_N[21] CMOS RF_N[20] RF_N[19] RF_N[18] RF_CP_WORD RF_N[17:14] RF_N[13] foLD RF_N[5:2] — Counter reset mode resets R & N counters. — IF charge pump current can be selected to high current (8X) or low current (1X) mode. ...
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... IF_R_CNTR[16: 32767 Division Ratio of the IF R Counter, IF_R_CNTR(RI S1M8831A/ Control Bits ...
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... If the control bits are 01(IF), 10, and 11(RF), data is transferred from the 24-bit shift register into the N/Frac-latch. N Counter consists of swallow counter (A counter; 3-bit for IF & S1M8831A RF and 4-bit for S1M8833), main counter (B counter; 7-bit for S1M8831A/33 RF and 12-bit for IF), and fractional counter (F counter; 17-bit for S1M8831A/33 RF) ...
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... RF_CTL_WORD CMOS[20:18] [23:21 Program Code RF_NA_CNTR TEST [23:20] RF Main Counter Division Ratio (B Counter) RF_NB_ CNTR[12:6] ; for S1M8831A/33 Division Ratio( 127 1 Division Ratio 127 (The division ratios less than 3 are prohibited) RF Swallow Counter Division Ratio (A Counter) RF_NA_CNTR[23:20] ; for S1M8831A ...
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... S1M8831A/33 RF Fractional Counter MSB RF_NA_CNTR TEST [23:20 Program Code RF Fractional Counter Value (F Counter) FRAC_ CNTR[18:2] ; for S1M8831A/33 RF Counter Value( 31488 -31488 Counter Value: -31488(2's complementary) to 31488 NOTE: For a negative integer, the counter value should be inputted as the corresponding 2's complementary binary code ...
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... Acronym LOW (0) IF_CP_GAIN 1X (100uA) Acronym LOW (0) RF_CP_LVL Select 16-level charge 8X 4X RF_N[16 S1M8831A/33 HIGH (1) Comments 8X (800uA) IF charge pump HIGH (1) Comments RF charge pump pump current 2X 1X RF_N[15] RF_N[14 ...
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... S1M8831A/33 Phase Detector Polarity (RF_CP_WORD/IF_CP_WORD; RF_N[13]/IF_N[17]) Depending on VCO characteristics, IF_N[17] and RF_N[13] bits should be set as follows: Control Bits IF_N[17] RF_N[13] 22 LOW (0) HIGH (1) Negative Slope Positive Slope Negative Slope Positive Slope VCO Characteristics VCO Output Frequency VCO Input Voltage FRACTIONAL-N RF/INTEGER-N IF DUAL PLL ...
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... The PLL returns to the active power-up mode when IF_N[20] and RF_N[22] become LOW. There are synchronous and asynchronous power-down modes for S1M8831A/33. The power-down bit IF_N[19] is used to select between synchronous and asynchronous power down. Synchronous power down mode occurs if IF_N[19] bit is HIGH and then the power down bit (RF_N[22] or IF_N[20]) becomes HIGH ...
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... S1M8831A/33 Reference Oscillator Input Control Control Words Control bits OSC IF_N[22] The reference oscillator frequency is provided from an external reference such as TCXO through the OSCin and OSCx pins. When the OSC bit is LOW, the oscillator input pins( OSCin and OSCx) drive the IF R and RF R counters separately ...
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... Operation Acronym LOW (0) Frac-N_SEL Reserved Acronym LOW (0) Speedy Lock CMOS Output OUT1 Voltage LOW OUT0 Voltage LOW 8X) is selected and otherwise to a tri-state. For using S1M8831A/33 HIGH (1) Comments IF Counter IF Reset RF Counter Reset RF HIGH (1) Comments Fractional-N Mode RF; PLL Mode Selection HIGH (1) Comments ...
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... LOW. Lock Detector (LD) There is analog mode for S1M8831A/33. The foLD bits, RF_N[5:2], are used to select the lock detection mode and to output the selected lock signal through the foLD pin. The foLD output becomes HIGH with narrow pulsed LOW while both RF and IF PLLs are locked and thereby the output should be low-pass filtered for a DC locked voltage HIGH ...
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... VCO : External VCO output frequency f OSC : External reference frequency (From external oscillator Preset divide ratio of programmable R counter (RF 32767 Preset modulus of dual modulus prescaler (S1M8831 RF: P=8, S1M8833 RF: P=16, IF: P= Preset value of main counter (S1M8831A/33 RF 126, IF 4095 Preset value of swallow counter division ratio (S1M8831 RF ...
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... S1M8831A/33 Serial Data Input Timing MSB DATA DATA[23] CLOCK LE Phase Detector and Charge Pump Characteristics Phase difference detection range: -2 When the positive-slope polarity of PFD is selected, IF_N[17] = HIGH or RF_N[13] = HIGH > DATA[22] DATA[10] DATA[ CWL < ...
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... Sensitivity limit is determined when the error of the divided RF output (fOLD) becomes 10Hz 1.0GHz 1000 S1M8831 Integer-N test mode VCO f = 1.6GHz 1600 16 1M8833 Integer-N test mode VCO 2. S1M8831A 51 100pF /33 OSC in LE DATA foLD CLOCK 12k 39k DD P 100pF 2.2 F 100pF PC Parallel Port S1M8831A/33 2 ...
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... NOTE: The role of Rin: Rin makes a large portion of VCO output power go to the load rather than the PLL. The value of Rin depends on the VCO power level VCO 10pF C3 C2 10pF 100pF GND f RF DGND S1M8831A/ GND 1000pF 56pF IF Out 56pF VCO C13 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL V P 100pF 0 ...
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... The S1M8831A/33 has external four power supply pins to supply on-chip bias, each for analog and digital blocks of RF and IF PLLs. Basically in doing PCB layout important that power supply lines should be separated from one another and thus coupling noises through the voltage supply lines can be minimized ...
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... S1M8831A/33 PACKAGE DIMENSIONS INDEX AREA 3.50 + 0.10 4X0.50 + 0.10 (0.05) #24 20X0.50 24X0.30 + 0.05 2X1.00 C 0.10 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL 1.00MAX 0.27 + 0.05 0. MARK 2X 0. ...