FAN6921 Fairchild Semiconductor, FAN6921 Datasheet
FAN6921
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FAN6921 Summary of contents
Page 1
... RT pin and external NTC resistor, internal over- temperature shutdown, V voltage for output OVP, and brown-in / out for AC input voltage UVP. The FAN6921 controller is available in a 16-pin small outline package (SOP). Operating Eco Temperature Range Status -40° ...
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... Application Diagram © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 Figure 1. Typical Application 2 www.fairchildsemi.com ...
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... Internal Block Diagram © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 Figure 2. Functional Block Diagram 3 www.fairchildsemi.com ...
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... CSPWM pin for the cycle-by-cycle current limit, current- mode control, and high / low line over-power compensation according to DET pin source current during PWM t © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 Figure 3. Marking Diagram Figure 4. Pin Configuration time. ...
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... PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired connection High-voltage startup. HV pin is connected to the AC line voltage through a resistor 16 HV (100kΩ t ypical) for providing a high charging current to V © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 capacitor www.fairchildsemi.com ...
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... The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 Parameter (3) (3) Parameter 6 Min. Max. ...
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... Range-Enable/ Disable Debounce t RANGE Time V Output Low Voltage of RANGE Pin I RANGE-OL Output High Leakage Current of I RANGE-OH RANGE Pin t PFC Maximum On Time ON-MAX-PFC © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0 unless otherwise specified. J Conditions 0.16V, DD DD-ON Gate Open V =15V, DD OPFC, OPWM=100kHz, ...
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... PFC Current Sense Section Threshold Voltage for Peak V CSPFC Current Cycle-by-Cycle Limit t Propagation Delay PD t Leading-Edge Blanking Time BNK CSPFC Compensation Ratio for A V THD © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 (Continued unless otherwise specified. J Conditions (4) RANGE=Open RANGE=Ground INVH REF RANGE=Open (4) ...
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... Restart Time RESTART-PFC Inhibit Time (Maximum Switching t INHIB Frequency Limit) PFC Enable/ Disable Function V ZCD-DIS Threshold Voltage PFC Enable/ Disable Function t ZCD-DIS Debounce Time © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 (Continued unless otherwise specified. J Conditions V = 25V DD V =15V, I =100mA ...
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... Minimum Off Time OFF-MIN Beginning of Green-On Mode Voltage Level Beginning of Green-Off Mode Voltage Level Hysteresis for Beginning of ΔV Green-Off Mode at FB Voltage G Level © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 (Continued unless otherwise specified. J Conditions CSPWM 0<V <0.9 CSPWM (4) FB>V ...
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... Leading-Edge Blanking Time ON-BNK CSPWM Pin Floating V V CS-FLOATING Clamped High Voltage The Delay Time once CS Pin t CS-H Floating © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 (Continued) ), unless otherwise specified. J Conditions RANGE Pin Internally Open RANGE Pin Internally Ground RANGE Pin Internally Open ...
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... Threshold Voltage for Two-level V RT-OTP-LEVEL Debounce Time t Debounce Time for OTP RT-OTP-H Debounce Time for Externally t RT-OTP-L Triggering Note: 4. Guaranteed by design. © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 (Continued) ), unless otherwise specified. J Conditions V <V RT RT-OTP-LEVEL 12 Min. Typ. Max. Units 125 140 ...
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... Temperature( Figure 9. Startup Current 2.60 2.55 2.50 2.45 2.40 -40 -25 - Temperature( Figure 11. PFC Output Feedback Reference Voltage © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 =25° 110 125 110 125 o C) Figure 110 125 ...
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... Temperature( Figure 17. Beginning of Green-On Mode at V 9.0 8.5 8.0 7.5 7.0 -40 -25 - Temperature( Figure 19. PWM Minimum Off-Time for V © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 (Continued) =25° 110 125 o C) Figure 14. PFC Peak Current Limit Voltage 50.0 48.0 46.0 44.0 42.0 40 110 125 ...
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... Figure 21. Lower Clamp Voltage of DET Pin 110 105 100 95 90 -40 -25 - Temperature( Figure 23. Internal Source Current of RT Pin © 2009 Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 (Continued) =25° 110 125 o C) Figure 22. Reference Voltage for Output Over ...
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... Multi-Vector Error Amplifier and THD Optimizer For better dynamic performance, faster transient response, and precise clamping on PFC output, FAN6921 uses a trans-conductance type amplifier with proprietary innovative multi-vector error amplifier (US Patent 6,900,623). The schematic diagram of this amplifier is shown in Figure 25. The PFC output voltage ...
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... Figure 31. Operation Waveforms of PFC Zero- Protection for PFC Stage PFC Output Voltage UVP and OVP (INV Pin) FAN6921 provides several kinds of protection for PFC stage. PFC output over- and under-voltage are essential for PFC stage. Both are detected and determined by INV pin voltage, as shown in Figure 32. When INV pin voltage is over 2 ...
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... COMP pin voltage, lower COMP voltage results in narrow PFC on-time, so that the energy converged is limited and the PFC output voltage decreases. When INV pin is lower than 1.2V, FAN6921 stops all PFC and PWM switching operation immediately until V voltage drops to turn-off voltage DD then raises to turn-on voltage again (UVLO) ...
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... V also decreases since auxiliary winding is coupled to primary winding. Once the V falls to negative, V (refer to Figure 39) and FAN6921 is forced to flow out a current I DET current. If this source current rises to a threshold current, PWM gate signal is sent out after a fixed delay time (200ns typical) ...
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... DET of the output diode and C AUX prevent this spike, a leading-edge blanking time is built- DET in to FAN6921 and a small RC filter is also recommended between the CSPWM pin and GND (e.g. 100Ω, 470pF). 20 becomes higher as well as AUX and the controller regulates the V ...
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... PWM transformer inductor; the voltage across on auxiliary winding is reflected from secondary winding and therefore the flat voltage on the DET pin is proportional to the output voltage. FAN6921 can sample this flat voltage level after a t perform output over-voltage protection. This t blanking time is used to ignore the voltage ringing from leakage inductance of PWM transformer ...
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... Open-Loop, Short-Circuit, and Overload Protection (FB Pin) Figure 45. FB Pin Open-Loop, Short Circuit, and Overload Protection Referring to Figure 45, outside of FAN6921, the FB pin is connected to the collector of transistor of an opto- coupler. Inside of FAN6921, the FB pin is connected to an internal voltage bias through a resistor around 5kΩ. ...
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... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/, © 2009 Fairchild Semiconductor Corporation FAN6921 • Rev. 1.0.0 Figure 46. 16-Pin Small Outline Package (SOIC) 23 www.fairchildsemi.com ...
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... Fairchild Semiconductor Corporation FAN6921 Rev. 1.0.0 24 www.fairchildsemi.com ...