ATA5760 ATMEL Corporation, ATA5760 Datasheet

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ATA5760

Manufacturer Part Number
ATA5760
Description
Ata5760 Uhf Ask/fsk Receiver
Manufacturer
ATMEL Corporation
Datasheet

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Features
1. Description
The ATA5760/ATA5761 is a multi-chip PLL receiver device supplied in an SO20 pack-
age. It has been especially developed for the demands of RF low-cost data
transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or
Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF trans-
mitter T5750. Its main applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in the frequency receiving
range of f
transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz
applications.
Figure 1-1.
Remote control transmitter
T5750
Two Different IF Receiving Bandwidth Versions Are Available
(B
Frequency Receiving Range of
f
30 dB Image Rejection
Receiving Bandwidth B
55 ppm Crystals
Fully Integrated LC-VCO and PLL Loop Filter
Very High Sensitivity with Power Matched LNA
High System IIP3 (–16 dBm), System 1-dB Compression Point (–25 dBm)
High Large-signal Capability at GSM Band
(Blocking –30 dBm at +20 MHz, IIP3 = –12 dBm at +20 MHz)
5V to 20V Automotive Compatible Data Interface
Data Clock Available for Manchester- and Bi-phase-coded Signals
Programmable Digital Noise Suppression
Low Power Consumption Due to Configurable Polling
Temperature Range –40°C to +105°C
ESD Protection 2 kV HBM, All Pins
Communication to Microcontroller Possible Via a Single Bi-directional Data Line
Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements
0
= 868 MHz to 870 MHz or f
IF
UHF ASK/FSK
XTO
= 300 kHz or 600 kHz)
0
= 868 MHz to 870 MHz or f
Power
PLL
System Block Diagram
VCO
amp.
Antenna
IF
= 600 kHz for Low Cost 90-ppm Crystals and B
0
= 902 MHz to 928 MHz
Antenna
0
ATA5760/
ATA5761
= 902 MHz to 928 MHz for ASK or FSK data
LNA
Remote control receiver
Demod.
IF Amp
UHF ASK/FSK
VCO
PLL
Control
XTO
IF
= 300 kHz for
1...5
µC
UHF ASK/FSK
Receiver
ATA5760
ATA5761
4896C–RKE–04/06

Related parts for ATA5760

ATA5760 Summary of contents

Page 1

... Low-cost Solution Due to High Integration Level with Minimum External Circuitry Requirements 1. Description The ATA5760/ATA5761 is a multi-chip PLL receiver device supplied in an SO20 pack- age. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel’ ...

Page 2

... Figure 1-2. Block Diagram CDEM SENS AVCC AGND DGND DVCC LNAREF LNA_IN LNA LNAGND ATA5760/ATA5761 2 FSK/ASK- Dem_out demodulator and data filter Rssi Limiter out RSSI IF Amp. Sensitivity- Polling circuit reduction control logic 4. Order f0 = 950 kHz/ 1 MHz FE LPF fg = 2.2 MHz Standby logic IF Loop- Amp. ...

Page 3

... Not connected, connect to GND Crystal oscillator XTAL connection Digital power supply Test pin, during operation at DVCC Bit clock of data stream Digital ground Selects polling or receiving mode; Low: receiving mode, High: polling mode Data output/configuration input ATA5760/ATA5761 DATA DGND DATA_CLK TEST 4 DVCC XTAL NC ...

Page 4

... XTO pulling of ±30 ppm has to be added. The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth specification of the 600 kHz version of ATA5760/ATA5761 if the T5750 has also a total LO tolerance of ±120 ppm. For the ATA5760N3 crystals with ±55 ppm total tolerance are needed for receiver and transmit- ter to cope with the reduced IF-bandwidth ...

Page 5

... LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver ATA5760/ATA5761 exhibits its highest sensitivity if the LNA is power matched. This makes the matching to an SAW filter as well antenna easier. ...

Page 6

... IF = 300 kHz version and IF = 600 kHz for ATA5760/ATA5761 and determined by the value of the external resistor R . The output of the comparator is fed into the digital control logic. By this S is connected to GND, the receiver switches to full sensitivity also possible to con- is connected the receiver operates at a lower sensitivity ...

Page 7

... The BR_Range is defined in the OPMODE register (refer to section of the Receiver” on page The ATA5760/ATA5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V ...

Page 8

... The XTO deviation of the ATA5760/ATA5761 is an additional deviation due to the XTO circuit. This devia- tion is specified to be ±30 ppm worst case for a crystal with fF crystal of ±90 ppm is used, the total deviation is ± ...

Page 9

... Transmit = 7.14063 MHz, T XTO = 6.77617 MHz 2.066 µs) for B Clk = 6.77587 MHz 2.066 µs) for B Clk BR_Range0: BR_Range1: BR_Range2: BR_Range3: ATA5760/ATA5761 4, the frequency of the crystal oscillator (f = 14/f giving T = 2.066 µs for f XTO Clk = 915 MHz is mainly Transmit = 1.961 µs) Clk = 600 kHz IF ...

Page 10

... OPMODE register. This function is desirable where several devices share a single data line and may also be used for microcontroller polling – via pin POLLING/_ON, the receiver can be switched on and off. ATA5760/ATA5761 10 Figure 8-4 on page 13, the receiver stays in polling mode in a continuous cycle of ...

Page 11

... Bit-check Bit check OK ? YES 1/2 Bit 1/2 Bit 1/2 Bit T Bit-check Bit-check mode ATA5760/ATA5761 5-bit word defined by Sleep0 to Sleep4 in OPMODE register Extension factor defined by XSleepStd according to Table 9 Basic clock cycle defined by fXTO and Pin MODE : Is defined by the selected baud rate range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register ...

Page 12

... The bit-check limits are determined by means of the formula below. T Lim_min T Lim_max Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. ATA5760/ATA5761 12 Figure 8-3, the time window for the bit check is defined by two separate time limits between the lower bit-check limit the check will be continued ...

Page 13

... Bit Bit-check Bit-check mode ATA5760/ATA5761 and T Lim_min Lim_max , defined according to the section DATA_H_min Figure 8-9 on page 15 illustrate the bit check for the Figure 8-9 on page Bit check ok 1/2 Bit ...

Page 14

... DATA. This eases the interrupt handling of a connected microcontroller. The maximum time period for DATA to stay Low is limited to T employed to ensure a finite response time in programming or switching off the receiver via pin DATA. T data stream. receiver has switched to receiving mode. ATA5760/ATA5761 14 1/2 Bit ...

Page 15

... DATA (see section edge-to-edge time period t T DATA_min 4896C–RKE–04/ DATA_min t ee Receiving mode Bit-check mode of the majority of these noise pulses is equal or slightly higher than ee . ATA5760/ATA5761 t DATA_min DATA_min DATA_L_max “Digital Noise Suppression” on page ee 21). The 15 ...

Page 16

... Figure 8-11. Timing Diagram of the OFF Command via Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial bi-directional data line ATA5760/ATA5761 16 Figure 8-10 on page 16 illustrates the timing of the OFF command (see 28). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not elapses. Note that the capacitive load at pin DATA is limited (see Sleep “ ...

Page 17

... Start-up mode illustrates how to set the receiver back to polling mode via pin POLL- illustrates how to set the receiver to receiving mode via the pin . As long as POLLING/_ON is held to Low, the values for T “Digital Noise Suppression” on page ATA5760/ATA5761 X X Receiving mode . After the positive ...

Page 18

... If the bit check is set the receiver is set to receiving mode via the pin POLLING/_ON, the data clock is available if the data clock control logic has detected the distance 2T (Start bit). Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit. ATA5760/ATA5761 18 Table 11-10 on page 26 Lim_min_2T = (Lim_min + Lim_max) – ...

Page 19

... Receiving mode, data clock control logic active Data Logical error (Manchester code violation) '1' '1' '1' '0' '1' '1' Receiving mode, data clock control logic active ATA5760/ATA5761 Data '1' '1' '0' '1' ' Delay P_Data_Clk Receiving mode, data clock control logic active < > ...

Page 20

... Data_Out, the data clock is issued after an additional delay t Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at pin DATA is exceeded, the data clock disappears (see section Figure 9-5. ATA5760/ATA5761 20 Data Bit check ok '1' '1' '1' ...

Page 21

... Delay1 t Delay (Table 11-9 on page 25) in the OPMODE register is set to 1 (default), the illustrates the behavior of the data output at the end of a data stream. Bit check ok Data Digital Noise Digital Noise Receiving mode, bit check aktive ATA5760/ATA5761 0. 0. ...

Page 22

... POLLING/_ON must be set to High. This way of suppressing the noise is recommended if the data stream is not Manchester or Bi-phase coded. Figure 10-4. Controlled Noise Suppression Bit check ok Serial bi-directional Preburst data line (DATA_CLK) POLLING/_ON Bit-check mode ATA5760/ATA5761 22 Data Bit-check mode t < < t Timing error ee Lim_min ...

Page 23

... LIMIT register Lim_min Lim_ Lim_ Lim_ Lim_ Lim_ min3 min2 min1 min0 max5 ATA5760/ATA5761 Table 11-3 on page 23 11-2, bit 1 defines if the receiver is set back to polling “Receiving Mode” on page 14 programmed. Bit 10 Bit 11 Bit 12 Bit 13 – – – – – Sleep X ...

Page 24

... BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits T 11-11 on page Table 11-4. Baud1 Table 11-5. Table 11-6. ATA5760/ATA5761 24 and T Lim_min 26. Effect of the configuration word BR_Range BR_Range Baud0 Baud-rate Range/Extension Factor for Bit-check Limits (XLim) BR_Range0 0 (application USA/Europe: BR_Range0 = 1 ...

Page 25

... Effect of the Configuration Bit XSleep X Sleep X SleepStd 0 1 Effect of the Configuration Bit Noise Suppression Noise_Disable 0 1 ATA5760/ATA5761 Start Value for Sleep Counter Sleep0 (T = Sleep X Sleep Sleep 0 (Receiver is continuously polling until a valid 0 signal occurs 2.1 ms for X Sleep Sleep 868.3 ms, 2 ...

Page 26

... Lim_max5 Lim_max4 Lim_max3 Note: 1. Lim_max is also used to determine the margins of the data clock control logic (see section ATA5760/ATA5761 26 Lim_min2 Lim_min1 Lim_min0 ...

Page 27

... Conservation of the Register Information The ATA5760/ATA5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to below the threshold voltage V tion registers in that condition. Once V reset period t To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. ...

Page 28

... ATA5760/ATA5761 Bit 1 Bit 2 ("0") ("1") (Register- (Start bit) select) Programming frame ATA5760/ ATA5761 R pup DATA 0 ... 20 V Input - Serial bi-directional data line and Figure 13- Bit 14 Bit 15 ("0") (" ...

Page 29

... Applicable R pup - BR_range B0 B1 1nF 100pF B2 B3 ATA5760/ATA5761 28) is designed for automotive requirements. It can up to 20V and is short-circuit-protected. at pin DATA and the L Applicable 5 470 k 1 220 k 1 120 k 1 ...

Page 30

... SENS DATA C14 2 19 IC_ACTIVE POLLING/_ON 18 3 CDEM DGND 17 DATA_CLK 39n AVCC TEST4 5 TEST1 C13 15 6 AGND DVCC 10n ATA5760 10 XTAL LNAREF 12 9 LNA_IN TEST3 11 TEST2 10 LNAGND C16 C17 5.6p 18p ±0.1p 5% np0 np0 Toko LL1608-FS4N7S 4.7nH, ±0.3nH ...

Page 31

... Sleep 1024 1024 1024 2.0662 2.0662 1.9607 1852 1852 1758 1059 1059 1049 1059 1059 1049 662 662 628 ATA5760/ATA5761 Min. Max. 6 1000 150 –55 +125 –40 +105 10 Value 100 = 915 MHz, unless otherwise specified. 0 Variable Oscillator Typ. Max. Min. Typ. ...

Page 32

... Pulse Maximum Low period at BR_Range = pin DATA BR_Range0 t DATA_L_max (see BR_Range1 Figure 8-9 on BR_Range2 page 15) BR_Range3 Delay to activate the start-up Ton1 mode (see Figure 9-3 on page 19) ATA5760/ATA5761 32 = 4.5V to 5.5V 868.3 MHz and 868.3 MHz f = 915 MHz RF RF Min. Typ. Max. Min. Typ. 0.45 0.45 0.24 0.24 0.14 0.14 ...

Page 33

... ATA5760/ATA5761 = 915 MHz, unless otherwise specified. 0 Variable Oscillator Max. Min. Typ Clk 18.6 8.5 T Clk 15. Clk 7. Clk 3.92 ...

Page 34

... Parameters Current consumption LNA, Mixer, Polyphase Lowpass and IF Amplifier (Input Matched According to Third-order intercept point LO spurious emission System noise figure LNA_IN input impedance 1 dB compression point Image rejection Maximum input level ATA5760/ATA5761 34 = 4.5V to 5.5V 868.3 MHz f RF Min. Typ. ...

Page 35

... MHz IF BR_Range0 BR_Range1 BR_Range2 BR_Range3 f = 868.3 MHz/915 MHz 950 kHz/989 kHz/1 MHz ASK Ref_ASK Ref ATA5760/ATA5761 = 868.3 MHz and f = 915 MHz, unless otherwise specified. 0 Symbol Min. Typ. f 866 VCO f 900 VCO L (fm) –140 –55 f –30ppm f XTO ...

Page 36

... IF filter compared 25°C, amb S/N ratio to suppress inband noise signals. Noise signals may have any modulation scheme Dynamic range RSSI amplifier ATA5760/ATA5761 36 = 4.5V to 5.5V Test Conditions 300 kHz version f = 868.3 MHz/915 MHz 950 kHz/989 kHz/1 MHz ...

Page 37

... Red Values relative Sense Sense Sense Sense R = 100 k Sense R = 120 k Sense R = 150 k Sense Red Ref_Red Red ATA5760/ATA5761 = 868.3 MHz and f = 915 MHz, unless otherwise specified. 0 Symbol Min. Typ. fcu_DF 0.11 0. CDEM 12 8.2 270 156 t ee_sig 89 50 2.8 3.4 fu 4.8 6.0 8.0 10.0 15 ...

Page 38

... Saturation voltage High IC_ACTIVE output - Saturation voltage Low - Saturation voltage High POLLING/_ON input - Low level input voltage - High level input voltage TEST 4 pin - High level input voltage TEST 1 pin - Low level input voltage ATA5760/ATA5761 38 = 4.5V to 5.5V Test Conditions ...

Page 39

... SO20 Tube, for 915 MHz ISM band, Pb-free, B Taped and reeled, for 915 MHz ISM band, Pb-free, SO20 B Taped and reeled, for 868 MHz ISM band, Pb-free, SO20 B 12.95 12.70 2.35 0.25 0.10 11. ATA5760/ATA5761 = 600 kHz IF = 600 kHz IF = 300 kHz IF 9.15 8.65 7.5 7.3 0.25 10.50 10.20 technical drawings according to DIN specifications ...

Page 40

... Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4896C-RKE-04/06 4896B-RKE-02/06 ATA5760/ATA5761 40 History Page 4: first paragraph changed Page 5: text changed Page 4.1 IF Filter: text changed Page 10: text changed Page 30: figures 14-1 and 14-2 changed Page 31: El ...

Page 41

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2006. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...

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