ATA5743 ATMEL Corporation, ATA5743 Datasheet

no-image

ATA5743

Manufacturer Part Number
ATA5743
Description
Ata5743 Uhf Ask/fsk Receiver
Manufacturer
ATMEL Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA5743
Manufacturer:
ATMEL
Quantity:
87 448
Part Number:
ATA5743
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATA5743P
Quantity:
26
Part Number:
ATA5743P3
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATA5743P3-TGQY
Manufacturer:
ATMEL
Quantity:
203
Part Number:
ATA5743P3-TGQY
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATA5743P3-TKQY
Manufacturer:
ATMEL
Quantity:
5 000
Part Number:
ATA5743P3-TKQY
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATA5743P3MFP
Manufacturer:
INF
Quantity:
2 966
Part Number:
ATA5743P6
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Features
Benefits
1. Description
The ATA5743 is a multi-chip PLL receiver device supplied in an SSO20 package. It
has been especially developed for the demands of RF low-cost data transmission sys-
tems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The
receiver is well suited to operate with Atmel's PLL RF transmitter U2741B. Its main
applications are in the areas of telemetering, security technology, and keyless-entry
systems. It can be used in the frequency receiving range of f
for ASK or FSK data transmission. All the statements made below refer to
433.92 MHz and 315 MHz applications.
Two Different IF Receiving Bandwidth Versions are Available (B
5V to 20V Automotive-Compatible Data Interface
IC Condition Indicator, Sleep or Active Mode
Data Clock Available for Manchester- and Bi-phase-coded Signals
Fully Integrated VCO
Supply Voltage 4.5V to 5.5V, Operating Temperature Range -40°C to +105°C
Single-ended RF Input for Easy Adaptation to /4 Antenna or Printed Antenna on PCB
ESD Protection According to MIL-STD. 883 (2KV HBM)
High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW
Front-end Filter; Up to 40 dB is Achievable with State-of-the-art SAWs
Communication to Microcontroller Possible Via a Single, Bi-directional Data Line
Power Management (Polling) is also Possible by Means of a Separate Pin Via the
Microcontroller
Programmable Digital Noise Suppression
SSO20 Package
Low Power Consumption Due to Configurable Self Polling with a
Programmable Time frame Check
High Sensitivity, Especially at Low Data Rates
Minimal External Circuitry Requirements, no RF Components on the PC Board Except
Matching to the Receiver Antenna
Sensitivity Reduction Possible Even While Receiving
Low-cost Solution Due to High Integration Level
0
= 300 MHz to 450 MHz
IF
= 300 kHz or 600 kHz)
UHF ASK/FSK
Receiver
ATA5743
Rev. 4839B–RKE–08/05

Related parts for ATA5743

ATA5743 Summary of contents

Page 1

... Low-cost Solution Due to High Integration Level 1. Description The ATA5743 is a multi-chip PLL receiver device supplied in an SSO20 package. It has been especially developed for the demands of RF low-cost data transmission sys- tems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF transmitter U2741B ...

Page 2

... Figure 2-1. System Block Diagram UHF ASK/FSK Remote Control Transmitter ATA575x XTO PLL VCO Power amp. 3. Pin Configuration Figure 3-1. Pinning SSO20 ATA5743 2 UHF ASK/FSK Remote Control Receiver ATA5743 Demod Antenna Antenna LNA VCO SENS 1 20 DATA IC_ACTIVE 2 19 POLLING/_ON CDEM 3 18 DGND ...

Page 3

... Ground VCO Crystal oscillator Digital power supply Selecting 433.92 MHz/315 MHz Low 4.90625 MHz (USA) XT0 High 6.76438 MHz (Europe) XT0 Bit clock of data stream Digital ground Selects polling or receiving mode Low: receiving mode High: polling mode Data output/configuration input ATA5743 3 ...

Page 4

... Figure 3-2. Block Diagram CDEM AVCC SENS AGND DGND MIXVCC LNAGND LNA_IN ATA5743 4 FSK/ASK Dem_out Demodulator and data filter RSSI Limiter out Sensitivity IF Amp reduction 4. Order LPF Standby logic 3 MHz IF Amp VCO LPF 3 MHz f LNA 64 Data DATA Interface POLLING/_ON TEST Polling circuit ...

Page 5

... determined, f can be calculated using XTO LO XTO and hereby of f XTO 820 C9 = 4.7 nF C10 = C10 S C9 and the IF frequency f using the following for ATA5743 LF . The L should be opti When LO = 100 kHz. Loop Figure 4-1 shows can- LO and IF 5 ...

Page 6

... LNA_IN. The input impedance of that pin is provided in the electrical parameters. The para- sitic board inductances and capacitances also influence the input matching. The RF receiver ATA5743 exhibits its highest sensitivity at the best signal-to-noise ratio (SNR) in the LNA. Hence, noise matching is the best choice for designing the transformation network. ...

Page 7

... MHz RF L2 TOKO LL2012 RF IN B3761 2 IN 47n GND 315 MHz 27p 25n C16 RF 100p IN 2.7p C17 47n TOKO LL2012 L3 F39NJ Figure 4-2 and Figure ATA5743 120n L3 TOKO LL2012 5 OUT LNAGND ATA5743 LNA_IN 4-3), the bond wire 7 ...

Page 8

... MHz. For other RF input frequencies refer to RF center frequency. The ATA5743 is available with two different IF bandwidths. ATA5743P3, the version with B = 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter U2741B is used. IF The receiver ATA5743P6 employs an IF bandwidth of B together with the U2741B in ASK and FSK mode ...

Page 9

... The BR_Range is defined in the OPMODE register (refer to section of the Receiver” on page The ATA5743 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V then, the sensitivity will be reduced ...

Page 10

... Receiving Characteristics The RF receiver ATA5743 can be operated with and without a SAW front-end filter typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in the 300-kHz bandwidth version of the ATA5743. FSK mode and the 600-kHz bandwidth version of the receiver exhibit similar behavior ...

Page 11

... Clk = 315 MHz is mainly Send = 2.0383 µs) Clk = 2.0697 µs) Clk and on the logical state of pin MODE. The XTO ). Clk is defined by the following for- XClk XClk Clk XClk Clk XClk Clk XClk Clk ATA5743 ) is XTO -dependent Clk 11 ...

Page 12

... OPMODE register. This function is desirable where several devices share a single data line and may also be used for microcontroller polling – via pin POLLING/_ON, the receiver can be switched on and off. ATA5743 12 Figure 6-2 on page 13, the receiver’s polling mode consists of a continuous cycle of ...

Page 13

... Bit-check on the number of bits to be checked (N ), and on the utilized data rate Bit-check If the bit check fails, the average time period for that check depends on the selected baud-rate range The Clk baud-rate range is defined by Baud0 and Baud1 in the OPMODE register ATA5743 13 ...

Page 14

... Manchester or Bi-phase is a good choice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge time t various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. ATA5743 14 1/2 Bit 1/2 Bit 1/2 Bit ...

Page 15

... Bit check ok 1/2 Bit Bit-check 0 T Sleep Sleep mode ATA5743 The mini- XClk “Digital Signal ) to Bit-check Figure 6-6 the bit Bit check ok 1/2 Bit 15 ...

Page 16

... The maximum time period for DATA to stay Low is limited to T employed to ensure a finite response time in programming or switching off the receiver via pin DATA. T data stream. receiver has switched to receiving mode. ATA5743 16 1/2 Bit ...

Page 17

... DATA (see section edge-to-edge time period t T DATA_min 4839B–RKE–08/ DATA_min t ee Receiving mode Bit-check mode of the majority of these noise pulses is equal or slightly higher than DATA_min DATA_min DATA_L_max “Digital Noise Suppression” on page ATA5743 t ee 22). The 17 ...

Page 18

... Figure 6-12. Timing Diagram of the OFF command via Pin POLLING/_ON IC_ACTIVE POLLING/_ON Data_out (DATA) Serial bi-directional data line ATA5743 18 Figure 6-11 illustrates the timing of the OFF command (see also “Programming the Configuration Register” on page elapses. Note that the capacitive load at pin DATA is limited (see Sleep “ ...

Page 19

... N Sleep and N will be ignored, but not deleted Sleep Bit-check 22). must be programmed to 31 Sleep Figure 6-14 on page Table 6-10 on page 27 and Table 6-11 on page ATA5743 . After the on2 . As long as Bit-check 20, 27). 19 ...

Page 20

... Figure 6-14. Timing Diagram of the Data Clock Dem_out Data_out (DATA) DATA_CLK Figure 6-15. Data Clock Disappears Because of a Timing Error Dem_out Data_out (DATA) DATA_CLK ATA5743 20 If the result for “Lim_min_2T” or “Lim_max_2T” is not an integer value, it will be rounded up. Figure 6-15 and Figure 6-16 on page Figure 6-17 on page Preburst ...

Page 21

... Logical error (Manchester code violation Receiving mode, bit check aktive Start bit Receiving mode, data clock control logic active (see Figure 6-18 on page X 29). When the level of Data_In is equal to the Delay2 “Data Interface” on page ATA5743 0 0 Delay1 . For the pup 22, . 29). 21 ...

Page 22

... This way of suppressing the noise is recommended if the data stream is Manchester or Bi-phase coded and is active after power on. Figure 6-22 on page 23 Note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the selected baud-rate range. ATA5743 22 Data_Out ...

Page 23

... Bit check ok Preburst Data Receiving mode, Bit-check data clock control mode logic active < T < > Lim_min_2T ee Lim_max_2T Digital noise Bit-check mode Figure 6-23 on page 24. If the bit Noise_Disable 26) will not be executed because the ATA5743 ) 23 ...

Page 24

... Configuration of the Receiver The ATA5743 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register con- tents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM) ...

Page 25

... Lim_max Lim_ Lim_ Lim_ Lim_ max4 max3 max2 max1 illustrate the effect of the individual configuration and T as shown in Table 6-10 on page 27 Lim_max Bit-check Number of Bits to be Checked 0 3 (default ATA5743 Bit 14 Bit 15 Noise Suppression 0 Noise_ Disable 1 0 Lim_max0 1 and 25 ...

Page 26

... Table 6-6. Table 6-7. Sleep4 ... 0 ... Table 6-8. Table 6-9. ATA5743 26 Effect of the Configuration Bit Modulation Modulation ASK/_FSK 0 1 Effect of the Configuration Word Sleep Sleep Sleep3 Sleep2 Sleep1 ... ... ... ... ... ... Effect of the Configuration Bit X ...

Page 27

... Note: 1. Lim_max is also used to determine the margins of the data clock control logic (see section 6.6.1 Conservation of the Register Information The ATA5743 has integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. As seen in drops below the threshold voltage V configuration registers in that condition ...

Page 28

... Data_out (DATA) X 6.6.2 Programming the Configuration Register Figure 6-25. Timing of the Register Programming IC_ACTIVE Out1 (µC) Data_out (DATA) X Serial bi-directional data line X Receiving mode ATA5743 28 is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be 28. V ThReset t Rst ...

Page 29

... LIMIT are set to the default values cancelled if present. 4839B–RKE–08/ ATA5743 R pup DATA Input - Interface Serial bi-directional data line Figure 6-25 on page 28 and Figure T : t1(min) is the minimum specified value for the relevant BR_Range Clk T Clk Microcontroller I/O Out1 microcontroller 6-26. ATA5743 29 ...

Page 30

... The applicable pull-up resistor R selected BR_range (see maximum load capacity at pin DATA is given in the separate document “Application Note RKE Design Kit (U2741B, U3741BM)”. The internal circuitry with respect to the pin DATA is similar in ATA5743 and U3741BM. Table 6-12. Figure 6-27. Application Circuit ...

Page 31

... 150 pF np0 10% 820 C10 4 X7R 5% X7R 5% IC_ACTIVE Sensitivity reduction 1 DATA 19 POLLING/_ON 18 17 DATA_CLK 16 6.7643 15 MHz C11 np0 150 pF 10% np0 820 C10 4 X7R X7R 5% 5% ATA5743 31 ...

Page 32

... Junction temperature Storage temperature Ambient temperature Maximum input level, input matched Thermal Resistance Parameters Junction ambient ATA5743 32 = 315 MHz with SAW Filter 150 k 10% ATA5743 1 20 SENS DATA 2 19 C14 IC_ACTIVE POLLING /_ON 3 18 CDEM DGND ...

Page 33

... Sig Sig f XTO 1.0 f 64/432.92 XTO 1.8 BR_Range0 3.2 BR_Range1 5.6 BR_Range2 10.0 BR_Range3 163 10 T XClk XClk 40 XClk 20 XClk ATA5743 Max. Unit 1/f /10 µs XTO 1/f /14 µs XTO 8 T µs Clk 4 T µs Clk 2 T µs Clk 1 T µs Clk Sleep X 1024 ms Sleep T Clk 896 ...

Page 34

... BR_Range3 after POR Programming delay period Synchronization pulse (see Figure 6-11 and Delay until the Figure 6-25) programming window starts Programming window ATA5743 34 = 4.5V to 5.5V 433.92 MHz and 6.76438 MHz Osc. 4.90625 MHz Osc. (MODE: 1) Symbol Min. Typ. Max. Min. 2152 2152 2120 ...

Page 35

... T Clk 2.04 0 65.2 65 XClk 32.6 32 XClk 16.3 16 XClk 8.2 8 XClk ATA5743 Typ. Max. Unit 512 T µs Clk 256 T µs Clk 128 T µs Clk 258 T µs Clk 449.5 T µs Clk 1 T µs XClk 1 T µs XClk 1 T µs ...

Page 36

... Spurs of the VCO VCO gain Loop bandwidth of the PLL Capacitive load at pin LF XTO operating frequency Series resonance resistor of the crystal Static capacitance at pin XTO to GND ATA5743 36 = 4.5V to 5.5V 433.92 MHz and Test Conditions Sleep mode (XTO and polling logic active) IC active (start-up-, bit check-, ...

Page 37

... P Ref_ASK -108 -110 -106.5 -108.5 -106 -108 -104 -106 P +2.5 Ref P +5.5 Ref +7.5 P +5.5 Ref +7.5 ATA5743 Max. Unit -113 dBm -111 dBm -110 dBm -108 dBm -112 dBm -110.5 dBm -110 dBm -108 dBm -1.5 dB -1.5 dB -1.5 dB -1.5 dB -1.5 dB ...

Page 38

... Input sensitivity FSK 300 kHz IF-filter Input sensitivity FSK 600 kHz IF-filter Sensitivity variation FSK for the full operating range compared 25° amb S ATA5743 38 = 4.5V to 5.5V 433.92 MHz and Test Conditions Input matched according to Figure 4-3 -3 BER 300 kHz f = 433 ...

Page 39

... CDEM 12 8.2 270 156 t ee_sig 2.8 3.4 u 4.8 6.0 8.0 10.0 15.0 19.0 P -71 -76 Ref_Red -67 -72 -80 -85 -76 -81 -72 -77 -68 -73 -81 -86 -77 -82 ATA5743 Max. Unit - 0.20 kHz 1000 µs 560 µs 320 µs 180 µs 4.0 kHz 7.2 kHz 12.0 kHz 23 ...

Page 40

... Saturation voltage Low - Saturation voltage High POLLING/_ON input - Low level input voltage - High level input voltage MODE input - Low level input voltage - High level input voltage TEST input - Low level input voltage ATA5743 40 = 4.5V to 5.5V 433.92 MHz and Test Conditions Sense ...

Page 41

... Ordering Information Extended Type Number ATA5743P3-TKQY ATA5743P3-TKSY ATA5743P6-TKQY ATA5743P6-TKSY ATA5743P3-TGQY ATA5743P3-TGSY ATA5743P6-TGQY ATA5743P6-TGSY 11. Package Information 4839B–RKE–08/05 Package Remarks SSO20 Taped and reeled, Pb-free, 300 kHz bandwidth SSO20 Tube, Pb-free, 300 kHz bandwidth SSO20 Taped and reeled, Pb-free, 600 kHz bandwidth ...

Page 42

... Package SO20 Dimensions in mm 0.4 1. 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4839B-RKE-08/05 ATA5743 42 12.95 12.70 2.35 0.25 0.10 11. History Put datasheet in a new template First page: Pb-free logo added ...

Page 43

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life © Atmel Corporation 2005 . All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...

Related keywords