WM8766 Wolfson Microelectronics plc, WM8766 Datasheet
WM8766
Available stocks
Related parts for WM8766
WM8766 Summary of contents
Page 1
... DAC DESCRIPTION The WM8766 is a multi-channel audio DAC ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. Three stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported ...
Page 2
... WM8766 DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION 28 LEAD SSOP ...............................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION – 28 LEAD SSOP...................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY ............................................................................................................ 7 MASTER CLOCK TIMING ............................................................................................. 7 DIGITAL AUDIO INTERFACE – MASTER MODE ......................................................... 8 DIGITAL AUDIO INTERFACE – SLAVE MODE ............................................................ 9 MPU INTERFACE TIMING ...
Page 3
... PIN CONFIGURATION 28 LEAD SSOP ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM8766GEDS/V - WM8766GEDS/RV -25 to +85 C Note: Reel quantity = 2,000 w MOISTURE PACKAGE SENSITIVITY LEVEL 28-lead SSOP MSL3 (Pb-free) 28-lead SSOP MSL3 (Pb-free, tape and reel) WM8766 PEAK SOLDERING TEMPERATURE 260 C 260 C PD Rev 4.1 July 2005 3 ...
Page 4
... WM8766 PIN DESCRIPTION – 28 LEAD SSOP PIN NAME 1 MODE Digital input 2 MCLK Digital input 3 BCLK Digital input/output 4 LRCLK Digital input/output 5 DVDD 6 DGND 7 DIN1 Digital input 8 DIN2 Digital input 9 DIN3 Digital input 10 DNC Do not connect 11 ML/I2S Digital input 12 MC/IWL Digital input 13 MD/DM Digital input ...
Page 5
... Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range Storage temperature after soldering Notes: 1. Analogue and digital grounds must always be within 0.3V of each other for normal operation of the device. w WM8766 MIN MAX -0.3V +5V -0.3V +7V DGND -0.3V DVDD +0.3V AGND -0.3V AVDD +0 ...
Page 6
... WM8766 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Analogue supply range AVDD, VREFP Ground AGND, VREFN, DGND Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device . ELECTRICAL CHARACTERISTICS Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, T ...
Page 7
... MCLKL t MCLKH t MCLKY A SYMBOL TEST CONDITIONS t MCLKH t MCLKL t MCLKY After MCLK stopped After MCLK re-started 48kHz, MCLK = 256fs unless MIN TYP MAX 1000 40:60 60: 0 Rev 4.1 July 2005 WM8766 UNIT MCLK cycle 7 ...
Page 8
... WM8766 DIGITAL AUDIO INTERFACE – MASTER MODE BCLK WM8766 LRCLK DAC DIN1/2/3 3 Figure 2 Audio Interface - Master Mode BCLK (Output) LRCLK (Output) DIN1/2/3 Figure 3 Digital Audio Data Timing – Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, T otherwise stated. ...
Page 9
... BCLK rising edge Table 3 Digital Audio Data Timing – Slave Mode w DSP/ DECODER t t BCH BCL t BCY LRH o = +25 C, Slave Mode 48kHz, MCLK = 256fs unless otherwise A TEST CONDITIONS WM8766 t LRSU MIN TYP MAX UNIT Rev 4 ...
Page 10
... WM8766 MPU INTERFACE TIMING ML/I2S MC/IWL MD/DM Figure 6 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, T PARAMETER MC/IWL rising edge to ML/I2S rising edge MC/IWL pulse cycle time MC/IWL pulse width low MC/IWL pulse width high MD/DM to MC/IWL set-up time ...
Page 11
... Vpor_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, PORB is asserted low whenever DVDD drops below the minimum threshold Vpor_off. SYMBOL V pord V por_on V por_off Table 5 Typical POR Operation (typical values, not tested) w MIN TYP MAX 0.3 0.5 0.8 1.3 1.7 2.0 1.3 1.7 2.0 WM8766 UNIT Rev 4.1 July 2005 11 ...
Page 12
... In Slave mode the WM8766 has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 768fs mode. The WM8766 is tolerant of phase variations or jitter on the master clock. Table 6 shows the typical master clock frequency inputs for the WM8766 ...
Page 13
... Enable IZD, MUTE becomes an output to indicate when IZD occurs. L=IZD not detected, H=IZD detected. 0.001 0.002 0.003 Time(s) 384fs 512fs 768fs 12.288 16.384 24.576 16.9340 22.5792 33.8688 18.432 24.576 36.864 36.864 Unavailable Unavailable DESCRIPTION 0.004 0.005 PD Rev 4.1 July 2005 WM8766 MID 0.006 13 ...
Page 14
... However if the pin is connected to a high impedance, or left floating, then when all three internal zero flags are raised the WM8766 will also drive a weak logic high signal on the MUTE pin (output impedance 10kOhms) which can be used to drive an external device not possible to perform analogue mute in Hardware mode. ...
Page 15
... MASTER AND SLAVE MODES The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DIN1/2/3 are always inputs to the WM8766 and DOUT is always an output. The default is Slave mode. In Slave mode, LRCLK and BCLK are inputs to the WM8766 DIN1/2/3 and LRCLK are sampled by the WM8766 on the rising edge of BCLK ...
Page 16
... Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned. LEFT JUSTIFIED MODE In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8766 on the first rising edge of BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right samples, see Figure 13. ...
Page 17
... Production Data RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8766 on the rising edge of BCLK preceding a LRCLK transition. LRCLK are high during the left samples and low during the right samples, see Figure 14. Figure 14 Right Justified Mode Timing Diagram ...
Page 18
... Figure 16 DSP Mode A Timing Diagram – DAC Data Input DSP MODE B In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8766 on the first BCLK rising edge following a LRCLK rising edge. DAC channel 1 right and DAC channels 2 and 3 data follow DAC channel 1 left data (Figure 17). ...
Page 19
... Production Data SOFTWARE CONTROL INTERFACE OPERATION The WM8766 is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin. 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data ...
Page 20
... WM8766 DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS DAC Control DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER Interface format is selected via the FMT[1:0] register bits: ...
Page 21
... Note: 32-bit right justified mode is not supported. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive bit data, the WM8766 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. ...
Page 22
... WM8766 DAC OUTPUT PHASE The DAC phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS DAC Phase DIGITAL ZERO CROSS-DETECT The digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN ...
Page 23
... Production Data SOFTWARE MODE The WM8766 can be muted in a number of different ways when in software mode (MODE pin pulled low). Refer to Figure 20 which shows a representation of the interaction between functions described below. Figure 20 Internal Mute Logic w WM8766 PD Rev 4.1 July 2005 23 ...
Page 24
... An overall MUTE to all channels can be applied by using the MUTEALL register. REGISTER ADDRESS MUTE PIN AS INPUT The WM8766 can be muted externally by driving the MUTE pin high. When the MUTE pin is driven low the device will never automute, although direct mutes can still be applied via the DMUTE or MUTEALL registers. ...
Page 25
... Table 12 Effect of DZFM on Mute Pin Decode When the Mute pin is used as an output, its logic level remains connected to the DZFM selector inside the chip (see figure 1). So, when the WM8766 drives the Mute pin high, the output DACs will also softmute as described by Table 13. ...
Page 26
... DAC DEEMPH POWERDOWN MODE AND DAC DISABLE Setting the PDWN register bit immediately powers down the DACs on the WM8766, overriding the DACD powerdown bits control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised ...
Page 27
... REGISTER ADDRESS Interface Control MASTER MODE SELECT Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK and BCLK are outputs and are generated by the WM8766. In Slave mode LRCLK and BCLK are inputs to WM8766. REGISTER ADDRESS Interface Control MASTER MODE LRCLK FREQUENCY SELECT In Master mode the WM8766 generates LRCLK and BCLK ...
Page 28
... WM8766 MUTE PIN DECODE The MUTE pin can either be used as an output or an input. When used as an input the MUTE pins action can be controlled by setting the DZFM bit to select the corresponding DAC for applying the MUTE to output its meaning is selected by the DZFM control bits. By default selecting the MUTE pin to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE pin to assert a softmute on DAC1 ...
Page 29
... Digital Attenuation data for all DAC channels in 0.5dB steps. See 11111111 Table 16 (0dB) Controls simultaneous update of all Attenuation Latches Not latched 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. L/RDAX[7:0] ATTENUATION LEVEL 00(hex (mute) 01(hex) -127dB : : : : : : FE(hex) -0.5dB FF(hex) 0dB WM8766 DESCRIPTION PD Rev 4.1 July 2005 29 ...
Page 30
... The device will be held in this reset state until a subsequent register write to any address is completed. REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8766 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B15 B14 B13 B12 ...
Page 31
... TEST CONDITIONS MIN DAC Filter 0.05 dB -3dB 0.555fs f > 0.555fs -60 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0 Figure 22 DAC Digital Filter Ripple –44.1, 48 and 96kHz 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0.6 0 Figure 24 DAC Digital Filter Ripple – 192kHz TYP MAX UNIT 0.444fs 0.487fs 0. 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) PD Rev 4.1 July 2005 WM8766 0.45 0.5 0.45 0.5 31 ...
Page 32
... WM8766 DIGITAL DE-EMPHASIS CHARACTERISTICS - Frequency (kHz) Figure 25 De-Emphasis Frequency Response (32kHz - Frequency (kHz) Figure 27 De-Emphasis Frequency Response (44.1KHz - Frequency (kHz) Figure 29 De-Emphasis Frequency Response (48kHz 0.5 0 -0.5 -1 -1 ...
Page 33
... DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Reference de-coupling capacitors for VMID and TESTREF pin. De-coupling for TESTREF. Filtering for VREFP. Omit if AVDD low noise. Filtering for VREFP. Use 0 if AVDD low noise. WM8766 PD Rev 4.1 July 2005 33 ...
Page 34
... DAC structure used in WM8766 produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment ...
Page 35
... B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS -C- 0.10 C SEATING PLANE MAX ----- 2.0 ----- 0.25 1.85 0.30 0.38 ----- 0.25 10.50 8.20 5.60 0. WM8766 DM007.E GAUGE PLANE 0. Rev 4.1 July 2005 35 ...
Page 36
... WM8766 IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability ...