WM8766 Wolfson Microelectronics plc, WM8766 Datasheet - Page 16

no-image

WM8766

Manufacturer Part Number
WM8766
Description
24-bit, 192khz 6-channel Dac
Manufacturer
Wolfson Microelectronics plc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM8766
Manufacturer:
NS
Quantity:
12
Part Number:
WM8766
Manufacturer:
SHARP
Quantity:
2
Part Number:
WM8766
Manufacturer:
WM
Quantity:
7 200
Part Number:
WM8766
Manufacturer:
WM
Quantity:
176
Part Number:
WM8766
Manufacturer:
ST
0
Part Number:
WM8766EDS
Manufacturer:
WOFLSON
Quantity:
20 000
Part Number:
WM8766G
Manufacturer:
WM
Quantity:
7 200
Part Number:
WM8766G
Manufacturer:
WM
Quantity:
20 000
Part Number:
WM8766GEDS
Manufacturer:
WOLFSON
Quantity:
20 000
Part Number:
WM8766GEDS/RV
Manufacturer:
WM
Quantity:
20 000
WM8766
w
AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters via the Digital Audio Interface. 5 popular interface
formats are supported:
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the
exception of 32 bit right justified mode, which is not supported.
In left justified, right justified and I
DIN1/2/3 inputs. Audio data for each stereo channel is time multiplexed with LRCLK indicating
whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the
beginning or end of the data words.
In left justified, right justified and I
times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low
for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the
above requirements are met.
In DSP modes A or B, all 6 DAC channels are time multiplexed onto DIN1. LRCLK is used as a
frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK
period is 6 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided
the rising edge is correctly positioned.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8766 on the first rising edge of
BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right
samples, see Figure 13.
Figure 13 Left Justified Mode Timing Diagram
Left Justified mode
Right Justified mode
I2S mode
DSP mode A
DSP mode B
2
S modes, the minimum number of BCLKs per LRCLK period is 2
2
S modes, the digital audio interface receives DAC data on the
PD Rev 4.1 July 2005
Production Data
16

Related parts for WM8766