WM8768 Wolfson Microelectronics plc, WM8768 Datasheet
WM8768
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WM8768 Summary of contents
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... DAC DESCRIPTION The WM8768 is a multi-channel audio DAC ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. Four stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported ...
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... WM8768 DESCRIPTION ................................................................................................................1 FEATURES......................................................................................................................1 APPLICATIONS ..............................................................................................................1 BLOCK DIAGRAM ..........................................................................................................1 TABLE OF CONTENTS ..................................................................................................2 PIN CONFIGURATION 28 LEAD SSOP ........................................................................3 ORDERING INFORMATION ...........................................................................................3 PIN DESCRIPTION – 28 PIN SSOP ...............................................................................4 ABSOLUTE MAXIMUM RATINGS..................................................................................5 RECOMMENDED OPERATING CONDITIONS ..............................................................6 MASTER CLOCK TIMING .......................................................................................................8 DIGITAL AUDIO INTERFACE – MASTER MODE ...................................................................8 DIGITAL AUDIO INTERFACE – SLAVE MODE ......................................................................9 MPU INTERFACE TIMING ....................................................................................................11 INTERNAL POWER ON RESET CIRCUIT ...
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... PIN CONFIGURATION 28 LEAD SSOP ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM8768GEDS -25 to +85 o WM8768GEDS/R -25 to +85 Note: Reel quantity = 2,000 w PACKAGE SENSITIVITY LEVEL 28-lead SSOP C (Pb-free) 28-lead SSOP C (lPb-free, tape and reel) WM8768 MOISTURE PEAK SOLDERING TEMPERATURE MSL3 260°C MSL3 260°C PD Rev 4.2 July 2005 3 ...
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... WM8768 PIN DESCRIPTION – 28 LEAD SSOP PIN NAME 1 MODE Digital input 2 MCLK Digital input 3 BCLK Digital input/output 4 LRCLK Digital input/output 5 DVDD 6 DGND 7 DIN1 Digital input 8 DIN2 Digital input 9 DIN3 Digital input 10 DIN4 Digital input 11 ML/I2S Digital input 12 MC/IWL Digital input 13 MD/DM Digital input ...
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... Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range Storage temperature after soldering Notes: 1. Analogue and digital grounds must always be within 0.3V of each other for normal operation of the device. w WM8768 MIN MAX -0.3V +5V -0.3V +7V DGND -0.3V DVDD +0.3V AGND -0.3V AVDD +0 ...
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... WM8768 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Analogue reference supply Analogue supply range Ground AGND, VREFN, DGND Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device. ELECTRICAL CHARACTERISTICS Test Conditions AVDD, VREFP = 5V, DVDD = 3 ...
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... Channel Separation (dB) - Also known as crosstalk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. 6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region. w WM8768 PD Rev 4.2 July 2005 7 ...
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... In this power-saving mode, all registers will retain their values and can be accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically powered up, but a write to the volume update register bit is required to restore the correct volume settings. DIGITAL AUDIO INTERFACE – MASTER MODE BCLK WM8768 LRCLK DAC DIN1/2/3/4 4 ...
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... DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK WM8768 LRCLK DAC DIN1/2/3/4 4 Figure 4 Audio Interface – Slave Mode DST DHT = +25 A TEST CONDITIONS DL DSP/ DECODER Master Mode 48kHz, MCLK = 256fs unless MIN TYP MAX Rev 4.2 July 2005 WM8768 UNIT ...
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... WM8768 BCLK LRCLK DIN1/2/3/4 Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T stated. PARAMETER SYMBOL Audio Data Input Timing Information BCLK cycle time t BCY BCLK pulse width high t BCH BCLK pulse width low t BCL ...
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... 48kHz, MCLK = 256fs unless otherwise stated A SYMBOL MIN t 60 SCS t 80 SCY t 30 SCL t 30 SCH t 20 DSU t 20 DHO t 20 CSL t 20 CSH t 20 CSS WM8768 t t CSL CSH t CSS t SCS LSB TYP MAX UNIT Rev 4.2 July 2005 11 ...
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... INTERNAL POWER ON RESET CIRCUIT Figure 7 Internal Power on Reset Circuit Schematic The WM8768 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used reset the digital logic into a default state after power up. The POR circuit is powered from DVDD and monitors DVDD. It asserts PORB low if DVDD is below a minimum threshold. ...
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... If there is a greater than 32 clocks error the interface defaults to 1152fs mode. WM8768 is tolerant of phase variations or jitter on the master clock. Table 6 shows the typical master clock frequency inputs for the WM8768. ...
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... WM8768 SAMPLING RATE (LRCLK) 128fs 32kHz 4.096 44.1kHz 5.6448 48kHz 6.144 96kHz 12.288 192kHz 24.576 Table 6 System Clock Frequencies Versus Sampling Rate HARDWARE CONTROL MODES When the MODE pin is held high, the following hardware modes of operation are available. MUTE AND AUTOMUTE OPERATION In both hardware and software modes, the MUTE pin controls the selection of MUTE directly, and can be used to enable and disable the automute function ...
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... However if the pin is connected to a high impedance, or left floating, then when all four internal zero flags are raised. the WM8768 will also drive a weak logic high signal on the MUTE pin (output impedance 10kOhms) which can be used to drive an external device not possible to perform analogue mute in Hardware mode. ...
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... Master and Slave modes DIN1/2/3/4 are always inputs to the WM8768. The default is Slave mode. In Slave mode, LRCLK and BCLK are inputs to the WM8768 (Figure 11). DIN1/2/3/4 and LRCLK are sampled by the WM8768 on the rising edge of BCLK. By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3/4 and LRCLK are sampled on the falling edge of BCLK ...
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... Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned. LEFT JUSTIFIED MODE In left justified mode, the MSB of DIN1/2/3/4 is sampled by the WM8768 on the first rising edge of BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right samples (Figure 13). ...
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... BCKIN DIN1/2/3/4 Figure 15 I DSP MODE A In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8768 on the second rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4 data follow DAC channel 1 left data (Figure 16). LRCIN ...
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... Production Data DSP MODE B In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8768 on the first BCLK rising edge following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4 data follow DAC channel 1 left data (Figure 17). LRCIN BCKIN DIN1 Figure 17 DSP Mode B Timing Diagram – ...
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... WM8768 SOFTWARE CONTROL INTERFACE OPERATION The WM8768 is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin. 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data ...
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... DSP Modes DEFAULT DESCRIPTION left/right/I S modes: LRCLK Polarity (normal normal LRCLK polarity 1: inverted LRCLK polarity In DSP mode DSP mode A 1: DSP mode B PD Rev 4.2 July 2005 WM8768 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right ...
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... Note: If 32-bit mode is selected in right justified mode, the WM8768 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive bit data, the WM8768 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. ...
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... Analogue mute can only be used in software mode and will cause the output of the selected DAC to perform an analogue mute that clamps the output of the DAC to VMID. This function is dependent in the IZD bit which is described in section INFINITE ZERO DETECT, later. w 0.001 0.002 0.003 Time(s) WM8768 0.004 0.005 0.006 with a time constant of MID PD Rev 4.2 July 2005 23 ...
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... WM8768 SOFTWARE MUTE MODES The WM8768 can be muted in a number of different ways when in software mode (MODE pin pulled low). Refer to Figure 20 which shows a representation of the interaction between functions described below. DMUTE4, DMUTE(2:0) DIN1 DIN2 DIN3 DIN4 MUTE (pin) Figure 20 Internal Mute Logic ...
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... Production Data DMUTE AND MUTEALL The WM8768 can be directly muted using the DMUTE and DMUTE4 register bits to control which channels are muted. The mute happens as soon as the serial write is performed. REGISTER ADDRESS DAC4 Control {DMUTE4,DMUTE [2:0]} Table 10 DAC Mute Control An overall MUTE to all channels can be applied by using the MUTEALL register. ...
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... WM8768 MUTE PIN AS INPUT The WM8768 can be muted externally by driving the MUTE pin high. When the MUTE pin is driven low the device will never automute, although direct mutes can still be applied via the DMUTE or MUTEALL registers. The DZFM bits are used to decode the operation of a MUTE pin (decides which channels will be affected by the logic level present on the MUTE pin) ...
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... Table 12 Effect of DZFM on Mute Pin Output When the Mute pin is used as an output, its logic level remains connected to the DZFM selector inside the chip (see figure 1). So, when the WM8768 drives the Mute pin high, the output DACs will also softmute as described by Table 13. ...
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... WM8768 INFINITE ZERO DETECT When it is set, the IZD register causes an analogue mute of the DAC channel output amplifier both when there are 1024 zeros on that channel’s DIN pin or when it is manually muted by DMUTE or MUTEALL. REGISTER ADDRESS DAC Channel Control This operation is only available in software mode and can sometimes create a very small click at the output of the device ...
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... Production Data POWERDOWN MODE AND DAC DISABLE Setting the PDWN register bit immediately powers down the DACs on the WM8768, overriding the DACD powerdown bits control bits. All trace of the previous input samples is removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised ...
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... WM8768 MASTER MODE SELECT Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK and BCLK are outputs and are generated by the WM8768. In Slave mode LRCLK and BCLK are inputs to WM8768. REGISTER ADDRESS Interface Control MASTER MODE LRCLK FREQUENCY SELECT In Master mode the WM8768 generates LRC and BCLK ...
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... Store RDA4 and update attenuation on all channels. 11111111 Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 16 (0dB) Not latched Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. WM8768 DESCRIPTION PD Rev 4.2 July 2005 31 ...
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... This reset will last either 2*MCLK periods or until another write is made to the serial interface. REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8768 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B15 B14 B13 ...
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... TEST CONDITIONS MIN 0.05 dB -3dB 0.555fs f > 0.555fs -60 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0 Figure 22 DAC Digital Filter Ripple –44.1, 48 and 96kHz 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0.6 0 Figure 24 DAC Digital filter Ripple – 192kHz TYP MAX UNIT 0.444fs 0.487fs 0. 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Frequency (Fs) PD Rev 4.2 July 2005 WM8768 0.45 0.5 0.45 0.5 33 ...
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... WM8768 DIGITAL DE-EMPHASIS CHARACTERISTICS - Frequency (kHz) Figure 25 De-Emphasis Frequency Response (32kHz - Frequency (kHz) Figure 27 De-Emphasis Frequency Response (44.1kHz - Frequency (kHz) Figure 29 De-Emphasis Frequency Response (48kHz 0.5 0 -0.5 -1 -1 ...
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... Table 18 External Components Description w DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Reference de-coupling capacitors for VMID. De-coupling for TESTREF1 Filtering for VREFP. Omit if AVDD low noise. Filtering for VREFP. Use 0 if AVDD low noise. WM8768 PD Rev 4.2 July 2005 35 ...
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... DAC structure used in WM8768 produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment ...
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... B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS -C- 0.10 C SEATING PLANE MAX ----- 2.0 ----- 0.25 1.85 0.30 0.38 ----- 0.25 10.50 8.20 5.60 0. WM8768 DM007.E GAUGE PLANE 0. Rev 4.2 July 2005 37 ...
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... WM8768 IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability ...