W90N740 Winbond Electronics Corp America, W90N740 Datasheet
W90N740
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W90N740 Summary of contents
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... The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference purposes of W90N740-based system design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. ...
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... EMC Descriptors ............................................................................................................63 7.5.2 EMC Register Mapping ......................................................................................................69 6.6 Network Address Translation Accelerator (NATA) ..................................................... 100 6.6.1 NAT Process Flow........................................................................................................101 6.6.2 NATA Registers Map....................................................................................................102 6.7 GDMA Controller ........................................................................................................ 112 6.7.1 GDMA Function Description .........................................................................................112 6.7.2 GDMA Registers Map...................................................................................................113 6.8 USB Host Controller ................................................................................................... 120 6.8.1 USB Host Controller Registers Map .............................................................................121 W90N740CD/W90N740CDG - II - ...
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... EBI/SDRAM Interface AC Characteristics ....................................................................175 7.3.2 EBI/External Master Interface AC Characteristics ........................................................176 7.3.3 EBI/(ROM/SRAM/External I/O) AC Characteristics ......................................................176 7.3.4 USB Transceiver AC Characteristics............................................................................177 7.3.5 EMC MII AC Characteristics.........................................................................................178 8. PACKAGE DIMENSIONS ....................................................................................................... 180 9. W90N740 REGISTERS MAPPING TABLE ............................................................................ 181 10. ORDERING INFORMATION .................................................................................................. 193 11. REVISION HISTORY .............................................................................................................. 193 W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - III - Revision A7 ...
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... GENERAL DESCRIPTION The W90N740 micro-controller is 16/32 bit, ARM7TDMI based RISC micro-controller for network as well as embedded applications. An integrated dual Ethernet MAC, the W90N740, is designed for use in broadband routers, wireless access points, residential gateways and LAN camera. The W90N740N is built around The ARM7TDMI CPU core designed by Advanced RISC Machines, Ltd. ...
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... Support TCP / UDP packets GDMA Controller • 2 Channel GDMA for memory-to-memory data transfers without CPU intervention • Increase or decrease source / destination address in 8-bit, 16-bit, or 32-bit data transfers • Supports 4-data burst mode to boost performance • Support external GDMA request W90N740CD/W90N740CDG - 2 - ...
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... Programmable as either low-active or high-active for 4 external interrupt sources • Priority methodology is encoded to allow for interrupt daisy-chaining • Automatically mask out the lower priority interrupt during interrupt nesting GPIO Controller • Programmable as an input or output pin W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 3 - Revision A7 ...
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... Programmable clock frequency, and the input frequency range is 3-30MHz; 15MHz is preferred. Operation Voltage Range • 2.7 – 3.6 V for IO Buffer • 1.62 – 1.98 V for Core Logic Operation Temperature Range • 0 – 70 Degree C Operating Frequency • 80 MHz (default) Package Type • 176-pin LQFP W90N740CD/W90N740CDG - 4 - ...
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... VSS33 35 nECS0 nECS1 nECS2 nECS3 40 nBTCS nSCS0 nSCS1 SDQM0 SDQM1 50 W90N740CD/W90N740CDG 165 160 155 150 W90N740 176-Pin LQFP Fig 3.1 176-Pin LQFP Pin Diagram Publication Release Date: September. 19, 2005 - 5 - 145 140 135 USBVDD DP DN 130 USBVSS GP9/nDSR GP8/nDTR GP7/nCD ...
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... External Bus Interface A [24:22] A [21:0] D [31:16] D [15:0] nWBE [3:0]/ SDQM [3:0] nSCS[1:0] NSRAS NSCAS NSWE MCKE NC NC EMREQ EMACK nWAIT NBTCS nECS[3:0] NOE Table 4 W90N740 Pins Assignment, continued W90N740CD/W90N740CDG 176-PIN LQFP ( 4 pins ) 164 163 pins ) pins ) 84-82 81-74, 72, 70,67-56 124-119, 117, 115-114, 111-105 104-103, 101, ...
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... RX0D [3:0] / R1B_RXD [1:0], R0_RXD [1:0] RX0_DV / R0_CRSDV RX0_ERR Ethernet Interface (1) MDC1 MDIO1 COL1 CRS1 TX1_CLK TX1D [3:0] / R1A_TX [1:0] TX1_EN /R1A_TXEN RX1_CLK / R1A_REFCLK RX1D [3:0] / R1A_RXD [1:0] RX1_DV / R1A_CRSDV RX1_ERR / R1A_RXERR W90N740CD/W90N740CDG 176-PIN LQFP ( 17 pins ) 142 143 151 152 150 149-146 144 153 159-157, 154 160 161 ( 17 pins ) ...
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... Table 4 W90N740 Pins Assignment, continued NAME USB Interface DP DN Miscellaneous GP [20:17] / nIRQ [3:0] GP16 / nXDREQ GP15 /nXDACK GP14 / TIMER1/ SPEED GP13 / TIMER0/ STDBY GP12 /nWDOG GP11 /RxD GP10 /TxD GP9/nDSR/nTOE GP8 /nDTR/FSE0 GP7 /nCD / VO GP6 /nCTS/ VM GP5 /nRTS/ VP GP4 /nRI / RCV GP [3:0] Power/Ground VDD18 ...
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... PIN DESCRIPTION Table 5.1 W90N740 Pins Description PIN NAME IO TYPE System Clock & Reset EXTAL I XTAL O MCLK O nRESET I TAP Interface internal pull- TCK ID down TMS IU internal pull-up TDI IU internal pull-up TDO O nTRST IU internal pull-up External Bus Interface A [24:22 [21: [31:16 [15:0] IO nWBE [3:0]/ ...
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... R0_RXD [1:0] RX0_DV / I R0_CRSDV RX0_ERR I W90N740CD/W90N740CDG MII Management Data Clock for Ethernet the reference - clock of MDIO0. Each MDIO0 data will be latched at the rising edge of MDC0 clock. MII Management Data I/O for Ethernet used to transfer MII - control and status information between PHY and MAC. ...
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... R1A_RXD[1:0] RX1_DV/ I R1A_CRSDV RX1_ERR / I R1A_RXERR W90N740CD/W90N740CDG DESCRIPTION MII Management Data Clock for Ethernet the reference - clock of MDIO1. Each MDIO1 data will be latched at the rising edge of MDC1 clock. MII Management Data I/O for Ethernet used to transfer MII - control and status information between PHY and MAC. ...
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... G USBVDD P USBVSS G DVDD18 P DVSS18 G AVDD18 P AVSS18 G W90N740CD/W90N740CDG Differential Positive USB IO signal - Differential Negative (Minus) USB IO signal - - External Interrupt Request or General Purpose I/O - External DMA Request or General Purpose I/O - External DMA Acknowledge or General Purpose I/O Timer 1 or General Purpose I/O. This pin is also used as SPEED, - Speed mode control for external USB transceiver Timer 0 or General Purpose I/O ...
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... A[31:0] Address Register Incrementer Register Bank (31 x 32-bit registers) (6 status registers Multiplier Barrel Shifter 32-bit ALU W90N740CD/W90N740CDG Address Instruction Decoder Instruction Pipeline Read Data Register Thumb Instruction Decoder Writer Data Register Fig 6.1 ARM7TDMI CPU Core Block Diagram Publication Release Date: September. 19, 2005 ...
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... System Memory Map W90N740 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The On-Chip Peripherals bank bytes top of the space (0xFFF0.0000 – 0xFFFF.FFFF) and the On-Chip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable space: 0x0~0x7FDF.FFFF if Cache ON ...
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... External I/O Bank 1 256KB - 32MB EBI Space External I/O Bank 0 256KB - 32MB SDRAM Bank 1 2MB - 64MB SDRAM Bank 0 2MB - 64MB ROM/FLASH 256KB - 32MB 0x0000.0000 W90N740CD/W90N740CDG Non-Cacheable space 0xFFFF.FFFF 512KB (Fixed) 0xFFF8.0000 512KB (Fixed) 0xFFF0.0000 10KB 0xFFE0.0000 External I/O Bank 3 External I/O Bank 2 External I/O Bank 1 ...
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... GPIO 6.2.3 Address Bus Generation The W90N740 address bus generation is depended on the required data bus width of each memory bank. The data bus width is determined by DBWD bits in each bank’s control register. The maximum accessible memory size of each external IO bank is 32M bytes . Table 6.2.2 Address Bus Generation Guidelines ...
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... The internal architecture is big endian. The little endian mode only support for external memory. The W90N740 can be configured as big endian or little endian mode by pull up or down the data D14 pin. If D14 is pull-up then little endian mode, otherwise big endian mode. ...
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... Connection of External Memory with Various Data Width The system diagram for W90N740 connecting with the external memory is shown in Fig. 6.2.4. Below tables (Table6.2.3 − Table6.2.14) show the program/data path between CPU register and the external memory using little / big endian and word/half-word/byte access. ...
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... SD BIT NUMBER 31 0 ABCD NWBE [3-0] / AAAA SDQM [3-0] BIT NUMBER 31 0 ABCD XD BIT NUMBER 31 0 ABCD EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG X = Don’t care HALF WORD 31 0 ABCD WA+2 WA XXAA XXAA XXXA ...
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... Sequence Table 6.2.5 and Table 6.2.6 Using big-endian and half-word access, Program/Data path between register and external memory Address whose LSB HAU = Address whose LSB nWBE [3-0] / SDQM [3- means active and U means inactive W90N740CD/W90N740CDG HALF WORD 31 0 CDAB WA ...
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... CPU REG DATA SA HAL BIT NUMBER BIT NUMBER HAL SDQM [3-0] AAUU BIT NUMBER BIT NUMBER EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG WORD HALF WORD ABCD ABCD HAU ...
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... ED XA BA0 nWBE [3-0] / AUUU SDQM [3-0] Bit Number Bit Number Ext. Mem Data Timing Sequence W90N740CD/W90N740CDG BAU = Address whose LSB WORD 31 0 ABCD BA1 BA2 BA3 ...
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... BIT NUMBER EXT. MEM DATA TIMING SEQUENCE Table 6.2.9 and Table 6.2.10 Using little-endian and word access, Program/Data path between register and external memory WA = Address whose LSB nWBE [3-0] / SDQM [3- means active and U means inactive W90N740CD/W90N740CDG WORD BA1 ...
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... ABCD SD BIT NUMBER 31 0 ABCD SDQM [3-0] AAAA BIT NUMBER 31 0 ABCD XD BIT NUMBER 31 0 ABCD EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG HALF WORD 31 0 ABCD WA+2 WA XXAA XXAA XXXA ...
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... BIT NUMBER BIT NUMBER HAL SDQM [3-0] UUAA BIT NUMBER BIT NUMBER EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG HAL = Address whose LSB is 0,4,8 Don’t care WORD HALF WORD ABCD ABCD HAU ...
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... ED XA BA0 NWBE [3-0] / UUUA SDQM [3-0] BIT NUMBER BIT NUMBER EXT. MEM DATA TIMING SEQUENCE W90N740CD/W90N740CDG BAU = Address whose LSB WORD 31 0 ABCD BA1 BA2 BA3 ...
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... The W90N740’s internal function blocks or external devices can request mastership of the system bus and then hold the system bus in order to perform data transfers. The design of W90N740 bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simultaneously request bus mastership ...
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... In Rotate Priority Mode (PRTMOD = 1), the IPEN and IPACT bits have no function (i.e. ignore). W90N740 used a round robin arbitration scheme ensures that all bus masters (except the External Bus Master, it always has the first priority) have equal chance to gain the bus and that a retracted master does not lock up the bus ...
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... REGISTER ADDRESS PDID 0xFFF0.0000 PACKAGE W90N740CD/W90N740CDG Pull-down Pull-up Pull-down Pull-up W90N740 normal operation D [9:8] R/W DESCRIPTION R Product Identifier Register R/W Arbitration Control Register R/W PLL Control Register R/W Clock Select Register R/W DESCRIPTION R Product Identifier Register CHPID 12 ...
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... PACKAGE [31:30] Package Type PACKAGE [31:30] 1 CHPID [23:0]: Chip identifier The Chip identifier of W90N740 is 0x90.0740 Arbitration Control Register (ARBCON) REGISTER ADDRESS 0xFFF0.0004 ARBCON RESERVED IPACT [2] ： Interrupt priority active When IPEN=”1”, this bit is set when the ARM core has an unmasked interrupt request. ...
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... PLL Control Register （PLLCON） W90N740 provides two options for clock generation - crystal and oscillator. The external clock via EXTAL input pin as the reference clock input of PLL module. The external clock can bypass the PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’ ...
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... NO：Output divider value (NO = OTDV) Clock Select Register (CLKSEL) REGISTER ADDRESS CLKSEL 0xFFF0.000C USBCKS RESERVED GDMA 7 6 USB TIMER UART W90N740CD/W90N740CDG PLL Output 480MHz Charge VCO Divider Pump FOUT (NO) OTDV[1:0] Fig 6.2.6 System PLL block diagram R/W DESCRIPTION R/W Clock Select Register ...
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... USB [7] ： USB clock enable bit 0 = Disable USB clock 1 = Enable USB clock TIMER [6] ： Timer clock enable bit 0 = Disable Timer clock 1 = Enable Timer clock UART [5] ： UART clock enable bit 0 = Disable UART clock 1 = Enable UART clock W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 33 - Revision A7 ...
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... External I/O Control with 8/16/32 bit external data bus Cost-effective memory-to-peripheral DMA interface SDRAM Controller supports external SDRAM & the maximum size of each device is 32MB ROM/FLASH & External I/O interface Support for PCMCIA 16-bit PC Card devices W90N740CD/W90N740CDG PLL OUTPUT CLOCK 0 58.594 KHz ...
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... AHB Bus Address Mapping to SDRAM Bus Note: * indicates the signal is not used; ** indicates the signal is fixed at logic 0 and is not used; The HADDR prefixes have been omitted on the following tables. A14 ~ A0 are the Address pins of the W90N740 EBI interface; W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 35 - ...
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... 128M 8Mx16 12x9 128M 4Mx32 12x8 256M* 32Mx8 13x10 256M* 16Mx16 13x9 W90N740CD/W90N740CDG A13 A12 A11 A10 A9 A8 (BS0 ...
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... 128M 8Mx16 12x9 128M 4Mx32 12x8 256M* 32Mx8 13x10 256M 16Mx16 13x9 W90N740CD/W90N740CDG A13 A12 A11 A10 (BS0 ...
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... C 9 128M 16Mx8 12x10 128M 8Mx16 12x9 128M 4Mx32 12x8 256M 32Mx8 13x10 256M 16Mx16 13x9 W90N740CD/W90N740CDG A13 A12 A11 A10 A9 A8 (BS0 ...
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... SDRAM Power Up Sequence The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. W90N740 supports the function of Power Up Sequence, that is, after system power on the W90N740 SDRAM Controller automatically executes the commands needed for Power Up Sequence and set the mode register of each bank to default value. The default value is: — ...
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... The W90N740 does not perform SDRAM refreshes when it is not the bus master. When an external bus master is in control of the external bus, and if it retains control for a long period of time, it must assume the responsibility of performing the necessary SDRAM refresh operations ...
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... The SDRAM Controller automatically provides an auto refresh cycle for every refresh period programmed into the REFRAT bits when the REFEN bit of each bank is set. WAITVT [2:1]: Valid time of nWAIT signal W90N740 recognizes the nEWAIT signal at the next “nth” MCLK rising edge after the nOE or nWBE active cycle. WAITVT bits determine the n. WAITVT [2:1] ...
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... W90N740CD/W90N740CDG BASADDR BTSIZE MCLK ...
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... This ROM/Flash bank is designed for a boot ROM. BASADDR bits determine its start address. The external data bus width is determined by the data bus signals D [13:12] power-on setting. BTSIZE [3:2] BUS WIDTH RESERVED PGMODE [1:0] ：Page mode configuration PGMODE [1: W90N740CD/W90N740CDG MCLK ...
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... There are two configuration registers SDCONF0、SDCONF1 for SDRAM bank 0、bank 1 respectively. Each bank can have a different configuration. REGISTER ADDRESS SDCONF0 0xFFF0.1008 SDCONF1 0xFFF0.100C W90N740CD/W90N740CDG Fig6.3.2 ROM/FLASH Read Operation Timing R/W DESCRIPTION R/W SDRAM bank 0 configuration register R/W SDRAM bank 1 configuration register - 44 - RESET VALUE 0x0000 ...
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... LATENCY [12:11] ：The CAS Latency of SDRAM bank 0/1 Defines the CAS latency of external SDRAM bank 0/1 LATENCY [12:11 COMPBK [7] ： Number of component bank in SDRAM bank 0/1 Indicates the number of component bank ( banks) in external SDRAM bank 0/ banks banks W90N740CD/W90N740CDG BASADDR ...
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... Timing Control Registers （SDTIME0/1） W90N740 offers the flexible timing control registers to control the generation and processing of the control signals and can achieve you use different speed of SDRAM REGISTER ADDRESS SDTIME0 0xFFF0.1010 0xFFF0.1014 SDTIME1 W90N740CD/W90N740CDG ...
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... Fig 6.3.4) tRCD [10: tRDL [7:6] ：SDRAM bank 0/1, Last data in to pre-charge command (see Fig 6.3.5) tRDL [7: W90N740CD/W90N740CDG 28 27 RESERVED 20 19 RESERVED tRP Publication Release Date: September ...
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... Row pre-charge time (see Fig 6.3.4) tRP [5: W90N740CD/W90N740CDG Fig 6.3.4 Access timing 1 of SDRAM - 48 - MCLK ...
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... Row active time (see Fig 6.3.4) tRAS [2: W90N740CD/W90N740CDG Fig 6.3.5 Access timing 2 of SDRAM Publication Release Date: September. 19, 2005 - 49 - MCLK Revision A7 ...
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... External I/O Control Registers（EXT0CON – EXT3CON） The W90N740 supports an external device control without glue logic very cost effective because address decoding and control signals timing logic are not needed. Using these control registers you can configure special external I/O devices for providing the low cost external devices control solution. ...
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... I/O bank 0~3 tCOH [10: W90N740CD/W90N740CDG MCLK 0 Reserved Publication Release Date: September. 19, 2005 ...
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... When ROM/Flash memory bank is configured, the access to its bank stretches chip selection time before the nOE or new signal is activated. tCOS [4: DBWD [1:0] ：Programmable data bus width for external I/O bank 0~3 DBWD [1: W90N740CD/W90N740CDG WIDTH OF DATA BUS MCLK 0 ...
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... DLH_CLK_SKEW DLH_CLK_REF [31:16]: Latch DLH_CLK clock tree by HCLK positive edge. (Read Only) SWPON [8]: SDRAM Initialization by Software trigger Set this bit will issue a SDRAM power on default setting command, this bit will be auto-clear by hardware. W90N740CD/W90N740CDG Fig 6.3.6 External I/O write operation timing R/W DESCRIPTION R/W Clock skew control register ...
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... Note: P-x means MCLKO shift “X” gates delay by refer HCLK positive edge, N-x means MCLKO shift “X” gates delay by refer HCLK negative edge. MCLK is the output pin of MCLKO, which is a internal signal on chip. W90N740CD/W90N740CDG GATE DLH_CLK_SKEW [7:4] DELAY P P-1 1 ...
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... Cache Controller The W90N740 has an 8KB Instruction cache, 2KB Data cache, and 8 words write buffer. The I-Cache and D-Cache are similar except the cache size. To enhance the hit ratio, these two caches are configured two-way set associative addressing. Each cache has four words cache line size. When a miss occurs, four words must be fetched consecutively from external memory ...
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... Instruction Cache Load and Lock The W90N740 supports a cache-locking feature that can be used to lock critical sections of code into I- Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down words. After a line is locked, it operates as a regular instruction SRAM ...
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... The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line is cleared to “0”. W90N740 has two unlock command, unlock line and unlock all. The unlock line operation is performed on a cache line granularity. In case the line is found in the cache unlocked and starts to operate as a regular valid cache line ...
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... Data Cache The W90N740 data cache (D-Cache 2KB two-way set associative cache. The cache organization is 64 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in memory. The cache is designed for buffer write-through mode of operation and a least recently used (LRU) replacement algorithm is used to select a line when no empty lines are available ...
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... The D-cache is automatically flushed during reset. 6.4.4.4. Data Cache Load and Lock The W90N740 supports a cache-locking feature that can be used to lock critical sections of data into D- Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The smallest space, which can be locked down words ...
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... Write Buffer The W90N740 provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data. The write buffer may be enabled or be disabled via the WRBEN bit in the CAHCNF register, and the buffer is disabled and flushed on reset. Drain write buffer To force data, which is in write buffer written to external main memory ...
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... ULKS [6] ：Unlock I-Cache/D-Cache single line Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be specified. ULKA [5] ：Unlock I-Cache/D-Cache entirely Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared to 0. W90N740CD/W90N740CDG R/W DESCRIPTION R/W Cache control register 28 ...
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... DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no operation is done and the command terminates with no exception. Cache Address Register (CAHADR) W90N740 Cache Controller supports one address register. This address register is used with the command set in the control register (CAHCON) by specifying instruction/data address. REGISTER ...
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... Ethernet MAC Controller (EMC) The W90N740 has two Ethernet MAC Controllers (EMC) for WAN/LAN application. Each EMC has its DMA controller, transmit FIFO, and receive FIFO. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM address register for entry address comparison, Transmit-FIFO, Receive-FIFO, TX/RX state machine controller and status controller ...
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... NATA 01 = Undefined W90N740 EMC receive DMA is allowed to access current descriptor if bit 31 is set the user driver program. If the entire frame is received successfully, then the ownership bit 31 is cleared and the ownership is granted to CPU. If NATA is enabled, NATA is also allowed to access current descriptor and bit 30 is set NATA when NATA is processing ...
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... The six bit values show current TCP status, and are transparent to the six bits in TCP header. The values are valid if current packet is TCP type and Hit is set. UCK_Err: TCP/UCKS Error TU_Err: TCP/UDP Error NH_Err: No Hit Error W90N740CD/W90N740CDG 28 27 TCP information 20 19 ...
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... The L/W value the hit port is internal port, and 0 if the hit port is external port. The value is valid if Hit is set. Hit: current packet is hit with NAT entry table The value current packet IP/port is in the entry list. If NAT is disabled, the bit is reserved. W90N740CD/W90N740CDG - 66 - ...
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... Tx Status O: Ownership bit 0 = CPU 1 = DMA W90N740 transmit DMA is allowed to access current descriptor if this bit is set to ‘1’ by the user driver program. If the entire frame is transmitted successfully, then the ownership bit is cleared and the ownership is granted to CPU. I: MAC transmit interrupt enable after transmission complete of the frame ...
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... Transmit is paused by a remote flow control command. SQE: SQE error After transmitting a frame, set if the fake collision signal did not come from the PHY for 1.6 µs. CCNT: Transmit Collision Count Count of collisions during transmission of a single packet. After 16 collisions, CCNT is 1111, and TXABT is set. W90N740CD/W90N740CDG ...
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... This set of registers is used to convey status/control information to/from the Ethernet MAC controller. These registers are used for loading commands generated by user, indicating transmit and receive status, buffering data to/from memory, and providing interrupt control. The registers used by W90N740 EMC (Ethernet MAC controller) are divided into three groups: • CAM REGISTERS • ...
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... DMA REGISTERS TXDLSA_0 0xFFF0.309C RXDLSA_0 0xFFF0.30A0 DMARFC_0 0xFFF0.30A4 TSDR_0 0xFFF0.30A8 RSDR_0 0xFFF0.30AC FIFOTHD_0 0xFFF0.30B0 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM9 Least Significant Word Register R/W CAM10 Most Significant Word Register R/W CAM10 Least Significant Word Register R/W CAM11 Most Significant Word Register R/W CAM11 Least Significant Word Register ...
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... R/W CAM2 Least Significant Word Register CAM3M_1 0xFFF0.3820 CAM3L_1 0xFFF0.3824 CAM4M_1 0xFFF0.3828 CAM4L_1 0xFFF0.382C R/W CAM4 Least Significant Word Register W90N740CD/W90N740CDG R/W DESCRIPTION R MAC Receive Pause count register R MAC Receive Pause Current Count Register R MAC Remote pause count register Current Transmit Descriptor Start Address ...
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... MCMDR_1 0xFFF0.388C R/W MAC Command Register MIID_1 0xFFF0.3890 MIIDA_1 0xFFF0.3894 MPCNT_1 0xFFF0.3898 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM5 Most Significant Word Register R/W CAM5 Least Significant Word Register R/W CAM6 Most Significant Word Register R/W CAM7 Most Significant Word Register R/W CAM7 Least Significant Word Register R/W CAM8 Most Significant Word Register ...
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... MAC in promiscuous mode, use CAMCMR_x settings to accept packets with all three types of destination address. The three types of destination address packets are as follows: 1. Station packets, xxxxxxx0-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx 2. Multicast packet, xxxxxxx1-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx-xxxxxxxx. (but x not all 1) 3. Broadcast packet, 11111111-11111111-11111111-11111111-11111111-11111111 W90N740CD/W90N740CDG R/W DESCRIPTION Transmit Descriptor Link List Start Address register ...
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... Set this bit to accept any packet with a broadcast address. AMP [1]: Accept Multicast Packet Default value: 0 Set this bit to accept any packet with a multicast address. AUP [0]: Accept Unicast Packet Default value: 0 Set this bit to accept any packet with a unicast address. W90N740CD/W90N740CDG DESCRIPTION 28 27 Reserved 20 19 ...
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... SDPZ bit in the MCMDR (MAC Command Register). The CPU uses the CAM address register as a database for destination address. To activate the CAM function, the appropriate enable bit has to be set in the CAMEN register. W90N740CD/W90N740CDG DESCRIPTION CAM enable register CAM enable register ...
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... CAMxL} : destination address (6 byte), with 2 bytes in CAMxL and 4 bytes in CAMxM, (CAM15M and CAM15L excluded). For example, if the address of Entry CAM 1 is desired to store 12-34-56-78-90-13, then the content of CAM1M is 12-34-56-78, and the content of CAM1L is 90-13-00-00. W90N740CD/W90N740CDG R/W DESCRIPTION CAM0 Most Significant Word Register CAM0 Least Significant Word Register ...
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... EnTDU EnLC EnTXABT Reserved EnCFR EnNATErr 7 6 EnMMP EnRP EnALIE W90N740CD/W90N740CDG Length / Type (2 bytes Op-code (2 bytes) (Most Significant Byte Op-code (2 bytes Operand (2 bytes) (Most Significant Byte Operand (2 bytes Reserved ...
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... Set this bit to enable the interrupt, which is generated when the MAC transmits, or discards one packet. EnTXEMP [17]: Enable Transmit FIFO Empty interrupt Default value: 0 Set this bit to enable the interrupt, which is generated when MAC transmit FIFO becomes empty (underflow) during a packet transmission. EnTXINTR [16]: Enable Interrupt on Transmit interrupt W90N740CD/W90N740CDG - 78 - ...
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... Set this bit to enable the interrupt, when the length field of the current frame is received. EnDFO [8]: Enable DMA receive frame over maximum size interrupt Default value: 0 Set this bit to enable the interrupt, when the received frame size is larger than the value stored in RXMS. W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 79 - Revision A7 ...
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... PHY asserted Rx_er during packet reception. EnRXINTR [0]: Enable Interrupt on Receive interrupt Default value: 0 Set this bit to enable the interrupt, which is generated if the reception of a packet caused an interrupt to be generated. This includes a good received interrupt, if the EnRXGD bit is set. W90N740CD/W90N740CDG - 80 - ...
Page 84
... EMC LAN port and EMC WAN port) to let the NAT accelerator work properly. LPCS [23]: Low Pin Count Package Switch Always set: 0 EnRMII [22]: Enable RMII Default value: 0 Set this bit to select RMII interface. W90N740CD/W90N740CDG R/W DESCRIPTION R/W MAC Command Register R/W MAC Command Register ...
Page 85
... TXON [8]: Transmit On Default value: 0 When this bit is set, the transmission process will be started. If the bit is clear, transmissions will stop after the current packet is transmitted completely. Users should change the bit when the MAC is in idle state. W90N740CD/W90N740CDG MAC 1 MAC 0 INTERFACE INTERFACE ...
Page 86
... Users should change the bit when the MAC is in idle state. MAC MII Management Data Register (MIID_0, MIID_1) W90N740 provides MII management function to let user access the registers of the external physical layer device. Setting options in MII management registers does not affect the MAC controller operation ...
Page 87
... W90N740CD/W90N740CDG DESCRIPTION Reserved MDCON RESET VALUE ...
Page 88
... MII management clock (MDC). MII Management Protocol ACCESS PREAMBLE START OPERATION 1… READ 1… WRITE W90N740CD/W90N740CDG MII MANAGEMENT PROTOCOL PHYADDR PHYREGADDR 10 AAAAA RRRRR 01 AAAAA RRRRR Publication Release Date: September. 19, 2005 ...
Page 89
... FIFO overflows, or because the RxON bit is cleared. This count does not include the number of packets rejected by the CAM. CRC error count (CECnt): The number of packets received with a CRC error. The counter will be increment at the end of packet reception if the MISTA indicates the CRC errors. W90N740CD/W90N740CDG R/W DESCRIPTION R/W ...
Page 90
... DMA Receive Descriptor Link List Start Address Register (RXDLSA_0, RXDLSA_1) REGISTER ADDRESS R/W RXDLSA_0 0xFFF0.30A0 R/W RXDLSA_1 0xFFF0.38A0 R W90N740CD/W90N740CDG R/W DESCRIPTION Transmit Descriptor Link-list Start Address register Transmit Descriptor Link-list Start Address register 28 27 TXDLSA 20 19 TXDLSA 12 11 TXDLSA TXDLSA DESCRIPTION ...
Page 91
... Default value: 0800h This value controls the maximum bytes for a received frame can be saved to memory. If the received frame size exceeds the value stored in this location and the EnDFO is set, an error interrupt is reported. The default maximum size is 2K bytes. W90N740CD/W90N740CDG R/W DESCRIPTION R/W DMA Receive Frame Control Register ...
Page 92
... RSDR [31:0]: Receive Start Demand Register Default value: Undefined While the receive descriptor is unavailable, the Rx state machine will enter Halt state. The user has to issue a write command with any data to Receive Start Demand register to restart the Rx operation. W90N740CD/W90N740CDG R/W DESCRIPTION W Transmit Start Demand Register ...
Page 93
... This value controls the transmit FIFO low threshold. If transmitting packet number is less than the setting value, Tx DMA will request the arbiter to get data from memory. W90N740CD/W90N740CDG R/W DESCRIPTION R/W FIFO Threshold Adjustment Register ...
Page 94
... This field will be set if access error from EMC to memory (for example, address undefined in system) is occurred. If the status and EnTxBErr in MIEN are both set, the EMC_TxINT will be triggered. If the status is set, the Tx operation will be ceased and the software reset to reset the EMC is recommended. W90N740CD/W90N740CDG DESCRIPTION MAC Interrupt Status Register ...
Page 95
... Set when MAC transmitting FIFO becomes empty (underflow) during a packet transmission. TXINTR [16]: Interrupt on Transmit Default value: 0 This bit is set if transmission of a packet caused an interrupt condition. CFR [14]: Control Frame Receive Default value: 0 This field will be set if the incoming frame is a MAC control frame (type==8808h). W90N740CD/W90N740CDG - 92 - ...
Page 96
... Default value: 0 This bit is automatically set when the missed error counter rolls over. RP [6]: Runt Packet Default value: 0 This bits is set, it indicates that the received packet length is less than 64 bytes (unless ARP in MCMDR is set). W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 93 - Revision A7 ...
Page 97
... EnRXGD bit in MIEN is set. MAC General Status Register (MGSTA_0, MGSTA_1) REGISTER ADDRESS MGSTA_0 0xFFF0.30B8 MGSTA_1 0xFFF0.38B8 Reserved 7 6 CCNT W90N740CD/W90N740CDG R/W DESCRIPTION R/W MAC General Status Register R/W MAC General Status Register 28 27 Reserved 20 19 Reserved 12 11 TXHA Reserved - 94 - RESET VALUE 0x0000 ...
Page 98
... The received pause count register, MRPC, stores the value of the 16-bit received pause counter read only. REGISTER ADDRESS R/W MRPC_0 0xFFF0.30BC MRPC_1 0xFFF0.38BC W90N740CD/W90N740CDG DESCRIPTION R MAC Receive Pause count register R MAC Receive Pause count register Publication Release Date: September. 19, 2005 - 95 - RESET VALUE 0x0000 ...
Page 99
... MRPC [15:0]: MAC Received Pause Count Register Default value: 0 The count value indicates the number of time slots the transmitter was paused due to the receipt of control pause operation packets from the MAC. W90N740CD/W90N740CDG 28 27 Reserved 20 19 Reserved 12 11 MRPC 5 4 ...
Page 100
... DMA Receive Frame Status Register (DMARFS_0, DMARFS_1) REGISTER ADDRESS DMARFS_0 0xFFF0.30C8 DMARFS_1 0xFFF0.38C8 W90N740CD/W90N740CDG R/W DESCRIPTION R MAC Remote pause count register R MAC Remote pause count register 28 27 Reserved 20 19 Reserved 12 11 MREPC ...
Page 101
... CTXDSA [31:0]: Current Transmit Descriptor Start Address Default value: 0000h This register reports the start address of the current transmit descriptor used by EMC. W90N740CD/W90N740CDG R/W DESCRIPTION Current Transmit Descriptor Start Address R Register Current Transmit Descriptor Start Address R Register 28 27 CTXDSA ...
Page 102
... CRXDSA [31:0]: Current Receive Descriptor Start Address Default value: 0000h This register reports the start address of the current receive descriptor used by EMC. W90N740CD/W90N740CDG DESCRIPTION Current Transmit Buffer Start Address Register Current Transmit Buffer Start Address Register 28 27 CTXBSA 20 19 ...
Page 103
... IP address, meaning that an inside IP address is replaced by the appropriate outside IP address, and vice versa. When the network is connected and SW Users can use NATA on W90N740 to speed up fixed (static) address translation and reduce software loading on processing layer-3 IP replacement. The NATA has 64 entries for users to initial replacement IP content and cooperate the 2 EMC ports to do NAT. The Features of the NATA： ...
Page 104
... The port number in the TCP/UDP header is replaced with new port number 3. Recalculate the IP checksum 4. Recalculate the TCP/UDP checksum NATA do MAC address replacement process : Replace MAC 0 and MAC 1 address in the MAC header (if Rx interrupt is enabled) W90N740CD/W90N740CDG NAT hit? Yes Rx triggers NAT processing NATA exit NAT process ...
Page 105
... This set of registers is used to convey status/control information to/from the NAT engine. These registers are used for loading commands generated by user, indicating network translation status, and providing interrupt control. The registers used by W90N740 NATA controller are divided into two groups: NATA Control and Status Registers Address Look Up and Replacement Entry Registers ...
Page 106
... LSAD63 0xFFF0.6FE8 LSPN63 0xFFF0.6FEC LSMAC63M 0xFFF0.6FF0 LSMAC63L 0xFFF0.6FF4 RSMAC63M 0xFFF0.6FF8 RSMAC63L 0xFFF0.6FFC W90N740CD/W90N740CDG R/W DESCRIPTION R/W NAT Masquerading IP Address Entry 0 R/W NAT Masquerading Port Number Entry 0 R/W Local Station IP Address Entry 0 R/W Local Station Port Number Entry 0 Local Station MAC Address Most Significant Word R/W Register for Entry 0 ...
Page 107
... Set this bit to start NAT function. The EMC Rx will begin packet parsing and lookup procedure if this bit is set. Clear this bit will stop all NAT operations. NAT Counter x Clear Register (NATCCLRx)( REGISTER ADDRESS NATCCLR0 0x7FF06010 | | NATCCLR3 0x7FF0601C W90N740CD/W90N740CDG R/W DESCRIPTION Reserved Reserved ...
Page 108
... CLRCNT23 CLRCNT22 CLRCNT21 6.6.2.3. NATCCLR2 CLREH47 CLREH46 CLREH45 CLREH39 CLREH38 CLREH37 CLRCNT47 CLRCNT46 CLRCNT45 7 6 CLRCNT39 CLRCNT38 CLRCNT37 W90N740CD/W90N740CDG 28 27 CLREH12 CLREH11 20 19 CLREH 4 CLREH CLRCNT12 CLRCNT11 CLRCNT4 CLRCNT3 28 27 CLREH28 CLREH27 20 19 CLREH20 CLREH19 12 11 CLRCNT28 ...
Page 109
... Otherwise there may be an error condition occurred, for example, when S/W program has changed entry data, but the previous hit packet is being processed, and cannot find replacement data. REGISTER ADDRESS NATCFG0 0x7FF06100 | | NATCFG63 0x7FF061FC W90N740CD/W90N740CDG CLREH60 CLREH59 CLREH52 CLREH51 ...
Page 110
... Set this bit to change comparison and replacement field in packets. For example, at the WAN port, destination address and port {DA, DP} is compared for inverse bit (I bit) clear bit is set, source address and port {SA, SP} is compared instead of {DA, DP applicable for IP filter. PxRE [4]: Port Number Replacement Enable at Entry x Default value: 0 W90N740CD/W90N740CDG 28 27 EHCNTx 20 ...
Page 111
... SA: (IP) address at source field SP: port number at source field DA: (IP) address at destination field DP: port number at destination field Data Content in the NATA table Field Entry 0 Entry …. …. Entry W90N740CD/W90N740CDG Field 1 Field …. … 108 - Field … ...
Page 112
... EXMACL (INMACM, INMACL)}: MAC address (6 bytes), with 2 bytes in EXMACL {LSMACxM, LSMACxL (RSMACxM, RSMACxL)}: MAC address (6 bytes), with 2 bytes in LSMACxL For example, if the External MAC address is desired to store 12-34-56-78-90-13, then the content of EXMACM is 12-34-56-78, and the content of EXMACL is 90-13-00-00. W90N740CD/W90N740CDG REPLACEMENT DA with LA (if AxRE set) ...
Page 113
... On the other hand, when the external MAC receive packet, its destination address and destination port number is compared. If the result is hit, then its destination address and destination port number are be replaced by LSADx and LSPNx, and the packet is transmitted to local MAC. W90N740CD/W90N740CDG 29 28 ...
Page 114
... MASPNx, LSPNx For example, if the masquerading address is 140.112.2.100 and the masquerading port number is 7500, then the value in MASAD is 8C-70-02-64, and the value in MASPN is 00-00-1D-4C. W90N740CD/W90N740CDG Address Byte Address Byte Address Byte 1 28 ...
Page 115
... The GDMA can be started by the software or external DMA request nXDREQ1/2/3. Software can also be used to restart the GDMA operation after it has been stopped. The CPU can recognize the completion of a GDMA operation by software polling or when it receives an internal GDMA interrupt. The W90N740 GDMA controller can increase source or destination address, decrease them as well, and conduct 8-bit (byte), 16-bit (half-word), or 32-bit (word) data transfers. The Features of the GDMA ： ...
Page 116
... RESERVED SABNDERR DABNDERR RESERVED 7 6 SAFIX DAFIX SADIR W90N740CD/W90N740CDG R/W DESCRIPTION Channel 0 Control Register Channel 0 Source Base Address Register Channel 0 Destination Base Address Register Channel 0 Transfer Count Register R Channel 0 Current Source Address Register Channel 0 Current Destination Address R Register R Channel 0 Current Transfer Count Register ...
Page 117
... Hardware sets this bit on a GDMA transfer failure Transfer error will generate GDMA interrupt AUTOIEN [19]: Auto initialization Enable 0 = Disables auto initialization 1 = Enables auto initialization, the GDMA_CSRC0/1,GDMA_CDST0/1,and GDMA_CTCNT0/1 registers are updated by the GDMA_SRC0/1,GDMA_DST0/1,and GDMA_TCNT0/1 registers automatically when transfer is complete. W90N740CD/W90N740CDG - 114 - ...
Page 118
... An atomic GDMA operation is defined as the sequence of GDMA operations until the transfer count register reaches zero. 6.7.2.1. BME [9]: Burst Mode Enable 0 = Disables the 4-data burst mode 1 = Enables the 4-data burst mode Ff there are 16 words to be transferred, and BME [9]=1, the GDMA_TCNT should be 0x04; W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 115 - Revision A7 ...
Page 119
... Channel 0/1 Source Base Address Register (GDMA_SRCB0, GDMA_SRCB1) The GDMA channel starts reading its data from the source address as defined in this source base address register. REGISTER ADDRESS GDMA_SRCB0 0xFFF0.4004 R/W Channel 0 Source Base Address Register GDMA_SRCB1 0xFFF0.4024 R/W Channel 1 Source Base Address Register W90N740CD/W90N740CDG R/W DESCRIPTION - 116 - RESET VALUE 0x0000.0000 0x0000.0000 ...
Page 120
... GDMA_DSTB1 0xFFF0.4028 R/W Channel 1 Destination Base Address Register DST_BASE_ADDR [31:0]: 32-bit Destination Base Address Channel 0/1 Transfer Count Register (GDMA_TCNT0, GDMA_TCNT1) REGISTER ADDRESS GDMA_TCNT0 0xFFF0.400C GDMA_TCNT1 0xFFF0.402C W90N740CD/W90N740CDG 28 27 SRC_BASE_ADDR [31:24 SRC_BASE_ADDR [23:16 SRC_BASE_ADDR [15: SRC_BASE_ADDR [7:0] DESCRIPTION 28 27 DST_BASE_ADDR [31:24] ...
Page 121
... Depending on the settings you make to the control register, the current source address will remain the same or will be incremented or decremented. Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1) REGISTER ADDRESS GDMA_CDST0 0xFFF0.4014 GDMA_CDST1 0xFFF0.4034 W90N740CD/W90N740CDG Reserved TFR_CNT [23:16] ...
Page 122
... The Current transfer count register indicates the number of transfer being performed. REGISTER ADDRESS GDMA_CTCNT0 0xFFF0.4018 GDMA_CTCNT1 0xFFF0.4038 CURRENT_TFR_CNT [23:0]: Current Transfer Count W90N740CD/W90N740CDG 28 27 CURRENT_DST_ADDR [31:24 CURRENT_DST_ADDR [23:16 CURRENT_DST_ADDR [15: CURRENT_DST_ADDR [7:0] R/W DESCRIPTION R Channel 0 Current Transfer Count Register R ...
Page 123
... The Features of the USB Host Controller: • USB 1.1 compatible • Open Host Controller Interface (OHCI) 1.1 compatible. • Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices. • Built-in DMA for real-time data transfer • Option for on-chip USB transceiver or external USB transceiver W90N740CD/W90N740CDG - 120 - ...
Page 124
... HcRhDescriptorA 0xFFF0.5048 HcRhDescriptorB 0xFFF0.504C HcRhStatus 0xFFF0.5050 HcRhPortStatus [1] 0xFFF0.5054 HcRhPortStatus [2] 0xFFF0.5058 W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Revision Register R/W Host Controller Control Register R/W Host Controller Command Status Register R/W Host Controller Interrupt Status Register R/W Host Controller Interrupt Enable Register R/W Host Controller Interrupt Disable Register Host Controller Communication Area ...
Page 125
... R/W 1-0 00b R/W W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Revision Register DESCRIPTION Revision Indicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification. (X.Y = XYh) Reserved. Read/Write 0's R/W DESCRIPTION R/W Host Controller Control Register DESCRIPTION ControlBulkServiceRatio Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1 where N is the number of Control Endpoints (i.e. ‘ ...
Page 126
... Register: HcControl BITS RESET R/W 7-6 00b R R R/W 31- W90N740CD/W90N740CDG DESCRIPTION HostControllerFunctionalState This field sets the Host Controller state. The Controller may force a state change from USPEND signaling from a downstream port. States are: 00 ESET 01 ESUME 10: U ...
Page 127
... R/W 15 17-16 00b 31- W90N740CD/W90N740CDG R/W DESCRIPTION Host Controller Command Status R/W Register DESCRIPTION HostControllerReset This bit is set to initiate the software reset. This bit is cleared by the Host Controller, upon completed of the reset operation. ControlListFilled Set to indicate there is an active ED on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List ...
Page 128
... R W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Interrupt Status Register DESCRIPTION SchedulingOverrun Set when the List Processor determines a Schedule Overrun has occurred. WritebackDoneHead Set after the Host Controller has written HcDoneHead to HccaDoneHead. StartOfFrame Set when the Frame Management block signals a ‘Start of Frame’ ...
Page 129
... R R R R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Interrupt Enable Register DESCRIPTION SchedulingOverrunEnable 0: Ignore 1: Enable interrupt generation due to Scheduling Overrun. WritebackDoneHeadEnable 0: Ignore 1: Enable interrupt generation due to Write-back Done Head. StartOfFrameEnable 0: Ignore 1: Enable interrupt generation due to Start of Frame. ResumeDetectedEnable 0: Ignore 1: Enable interrupt generation due to Resume Detected. ...
Page 130
... R R R R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Interrupt Disable Register DESCRIPTION SchedulingOverrunEnable 0: Ignore 1: Disable interrupt generation due to Scheduling Overrun. WritebackDoneHeadEnable 0: Ignore 1: Disable interrupt generation due to Write-back Done Head. StartOfFrameEnable 0: Ignore 1: Disable interrupt generation due to Start of Frame. ResumeDetectedEnable 0: Ignore 1: Disable interrupt generation due to Resume Detected. ...
Page 131
... Host Controller Control Head ED Register (HcControlHeadED) REGISTER ADDRESS HcControlHeadED 0xFFF0.5020 Register: HcControlHeadED BITS RESET R/W 3 31-4 0h R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Communication Area Register 0x0000.0000 DESCRIPTION R/W DESCRIPTION R/W Host Controller Period Current ED Register DESCRIPTION Reserved. Read/Write 0's PeriodCurrentED Pointer to the current Periodic List ED. R/W DESCRIPTION R/W Host Controller Control Head ED Register DESCRIPTION Reserved ...
Page 132
... Pointer to the Bulk List Head ED. Host Controller Bulk Current ED Register (HcBulkCurrentED) REGISTER ADDRESS HcBulkCurrentED 0xFFF0.502C Register: HcBulkCurrentED BITS RESET R/W 3 31-4 0h R/W W90N740CD/W90N740CDG R/W DESCRIPTION Host Controller Control Current ED R/W Register DESCRIPTION Reserved. Read/Write 0's ControlCurrentED Pointer to the current Control List ED. R/W DESCRIPTION R/W Host Controller Bulk Head ED Register 0x0000.0000 DESCRIPTION R/W DESCRIPTION ...
Page 133
... Register: HcFmInterval BITS RESET R/W 13-0 2EDFh R/W 15- 30-16 31 W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Done Head Register DESCRIPTION Reserved. Read/Write 0's DoneHead Pointer to the current Done List Head ED. R/W DESCRIPTION R/W Host Controller Frame Interval Register DESCRIPTION FrameInterval This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999 is stored here ...
Page 134
... Register: HcFmNumber BITS RESET R/W 15 31- W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Frame Remaining Register DESCRIPTION FrameRemaining When the Host Controller is in the U decrements each 12 MHz clock period. When the count reaches 0, (end of frame) the counter reloads with FrameInterval. loads when the Host Controller transitions into U Reserved ...
Page 135
... Register: HcLSThreshold BITS RESET R/W 11-0 628h R/W 31- W90N740CD/W90N740CDG R/W DESCRIPTION R/W Host Controller Periodic Start Register 0x0000.0000 DESCRIPTION PeriodicStart This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. Reserved. Read/Write 0's R/W DESCRIPTION Host Controller Low Speed Threshold ...
Page 136
... R R/W 23- 31-24 01h R/W W90N740CD/W90N740CDG R/W DESCRIPTION Host Controller Root Hub Descriptor A R/W Register DESCRIPTION NumberDownstreamPorts table of none-4 supports two downstream ports. PowerSwitchingMode Global power switching mode implemented in HYDRA-2. This bit is only valid when NoPowerSwitching is cleared. This bit should be written '0 Global Switching ...
Page 137
... Root Hub. These bits should not be written during normal operation. Register Address HcRhDescriptorB 0xFFF0.504C Register: HcRhDescriptorB Bits Reset R/W 15-0 0000h R/W 31-16 0000h R/W W90N740CD/W90N740CDG R/W Description Host Controller Root Hub Descriptor B R/W Register Description DeviceRemoveable table of none-4 ports default to removable devices Device not removable 1 = Device removable Port Bit relationship 0 : Reserved 1 : Port Port 2 ...
Page 138
... R R R/W 30- W90N740CD/W90N740CDG R state. SB ESET R/W Description R/W Host Controller Root Hub Status Register Description (Read) LocalPowerStatus Not Supported. Always read '0'. (Write) ClearGlobalPower Writing a '1' issues a ClearGlobalPower command to the ports. Writing a '0' has no effect. OverCurrentIndicator This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection and OverCurrentProtectionMode are cleared ...
Page 139
... R/W W90N740CD/W90N740CDG R state. SB ESET R/W Description R/W Host Controller Root Hub Port Status [1] R/W Host Controller Root Hub Port Status [2] Description (Read) CurrentConnectStatus device connected Device connected. NOTE: If DeviceRemoveable is set (not removable) this bit is always '1'. (Write) ClearPortEnable Writing '1' a clears PortEnableStatus. Writing a '0' has no effect. ...
Page 140
... R R R/W 31- W90N740CD/W90N740CDG DESCRIPTION Reserved. Read/Write 0's (Read) PortPowerStatus This bit reflects the power state of the port regardless of the power switching mode Port power is off Port power is on. Note: If NoPowerSwitching is set, this bit is always read as '1'. (Write) SetPortPower Writing a '1' sets PortPowerStatus. Writing a '0' has no effect. ...
Page 141
... Even, odd, or no-parity bit generation and detection -- 1-, 1&1/2, or 2-stop bit generation -- Baud rate generation • Break generation and detection • False start bit detection • Parity, overrun, and framing error detection • Full prioritized interrupt system controls W90N740CD/W90N740CDG - 138 - ...
Page 142
... ADDRESS R/W 0xFFF8.0000 RBR 7 6 8-bit Received Data [7:0] By reading this register, the UART will return an 8-bit data received from SIN pin (LSB first). W90N740CD/W90N740CDG DESCRIPTION R Receive Buffer Register (DLAB = 0) W Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) ...
Page 143
... Mask off Irpt_MOS 1 = Enable Irpt_MOS RLSIE [2]: Receive Line Status Interrupt (Irpt_RLS) Enable 0 = Mask off Irpt_RLS 1 = Enable Irpt_RLS THREIE [1]: Transmit Holding Register Empty Interrupt (Irpt_THRE) Enable 0 = Mask off Irpt_THRE 1 = Enable Irpt_THRE W90N740CD/W90N740CDG R/W DESCRIPTION W Transmit Holding Register (DLAB = 8-bit Transmitted Data ...
Page 144
... Baud Rate Divisor (High Byte) [7:0] The high byte of the baud rate divider This 16-bit divider {DLM, DLL} is used to determine the baud rate as follows Baud Rate = Crystal Clock / {16 * [Divisor + 2]} Note: This definition is different from 16550 W90N740CD/W90N740CDG R/W DESCRIPTION Divisor Latch Register (LS) R/W (DLAB = 1) 5 ...
Page 145
... Second out (Irpt_TOUT) Transmitter Holing 0010 Third Register Empty (Irpt_THRE) MODEM Status 0000 Fourth (Irpt_MOS) Note: These definitions of bit 7, bit 6, bit 5, bit 4 are different from the 16550. W90N740CD/W90N740CDG R/W DESCRIPTION R Interrupt Identification Register DMS INTERRUPT SOURCE None None Overrun error, parity error, framing ...
Page 146
... FME [0]: FIFO Mode Enable Because UART is always operating in the FIFO mode, writing this bit has no effect while reading always gets logical one. This bit must be 1 when other FCR bits are written to; otherwise, they will not be programmed. W90N740CD/W90N740CDG R/W DESCRIPTION W FIFO Control Register ...
Page 147
... One “ STOP bit” is generated in the transmitted data 1 = One and a half “ STOP bit” is generated in the transmitted data when 5-bit word length is selected; Two “ STOP bit” is generated when 6-, 7- and 8-bit word length is selected. W90N740CD/W90N740CDG R/W DESCRIPTION Line Control Register ...
Page 148
... RTS#[1]: Complement version of RTS# (Request-To-Send) signal DTR#[0]: Complement version of DTR# (Data-Terminal-Ready) signal Writing 0x00 to MCR, the DTR#, RTS#, nOUT1# and OUT2# bit are set to logic 1’s; Writing 0x0f to MCR, the DTR#, RTS#, nOUT1# and OUT2# bit are reset to logic 0’s. W90N740CD/W90N740CDG Character length 5 bits 6 bits ...
Page 149
... FEI [3]: Framing Error Indicator This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU reads the contents of the LSR. W90N740CD/W90N740CDG R/W Description R ...
Page 150
... Complement version of data set ready (DSR#) input CTS#[4]: Complement version of clear to send (CTS#) input DDCD [3]: DCD# State Change This bit is set whenever DCD# input has changed state, and it will be reset if the CPU reads the MSR. TERI [2]: Tailing Edge of RI# W90N740CD/W90N740CDG R/W DESCRIPTION R MODEM Status Register 4 3 ...
Page 151
... The time out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word. Once the content of time out counter (TOUT_CNT) is equal to that of time out interrupt comparator (TOIC), a receiver time out interrupt (Irpt_TOUT) is generated if TOR [7] = IER [ new incoming data word or RX FIFO empty clears Irpt_TOUT. W90N740CD/W90N740CDG R/W DESCRIPTION R/W ...
Page 152
... The watchdog timer will set the WTIF each time a time-out occurs. The WTIF can be polled to check the status, and software can restart the timer by setting the WTR. W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 149 - ...
Page 153
... CE [30]: Counter Enable 0 = Stops counting 1 = Starts counting IE [29]: Interrupt Enable 0 = Disables timer interrupt 1 = Enables timer interrupt. If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter decrements to zero. MODE [28:27]: Timer Operating Mode W90N740CD/W90N740CDG R/W/C DESCRIPTION R/W Timer Control Register 0 R/W Timer Control Register 1 R/W ...
Page 154
... TIC [23:0]: Timer Initial Count This is a 24-bit value representing the initial count. Timer will reload this value whenever the counter is decremented to zero. W90N740CD/W90N740CDG TIMER OPERATING MODE DESCRIPTION R/W Timer Initial Control Register 0 R/W Timer Initial Control Register RESERVED 20 ...
Page 155
... TDR [23:0]: Timer Data Register The current count is registered in this 24-bit value. Timer Interrupt Status Register (TISR) REGISTER ADDRESS TISR 0xFFF8.1018 TIF1 [1]: Timer Interrupt Flag 1 W90N740CD/W90N740CDG R/W/C DESCRIPTION R Timer Data Register 0 R Timer Data Register RESERVED 20 19 TDR [23:16 TDR [15:8] ...
Page 156
... ICE debug mode acknowledge enable 0 = When DBGACK is high, the timer clock will be held matter what DBGACK is high or not, the timer clock will not be held RESERVED [8 Put the watchdog time in the normal operating mode W90N740CD/W90N740CDG R/W/C DESCRIPTION Watchdog Timer Control Register R/W ...
Page 157
... Watchdog timer reset does not occur 1 = Watchdog timer reset occurs WTRE [1]: Watchdog Timer Reset Enable Setting this bit will enable the watchdog timer reset function Disable watchdog timer reset function 1 = Enable watchdog timer reset function WTR [0]: Watchdog Timer Reset W90N740CD/W90N740CDG INTERRUPT TIME-OUT 21 2 clocks 22 2 ...
Page 158
... FIQ and the IRQ by setting the F and I bits in the current program status register (CPSR). The W90N740 incorporates the advanced interrupt controller (AIC) that is capable of dealing with the interrupt requests from a total of 32 different sources. Currently, only 18 interrupt sources are defined ...
Page 159
... Interrupt Sources The table as shown below lists all the interrupt sources originated from internal peripherals and external devices. Please be careful that interrupt channel 0 and all that beyond 18 are undefined in this implementation. Table 6.11.1 W90N740 Interrupt Sources CHANNEL NAME 1 WDTINT 2 nIRQ0 3 nIRQ1 4 nIRQ2 ...
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... AIC_IPER 0xFFF8.210C AIC_ISNR 0xFFF8.2110 AIC_IMR 0xFFF8.2114 AIC_OISR 0xFFF8.2118 AIC_MECR 0xFFF8.2120 0xFFF8.2124 AIC_MDCR 0xFFF8.2128 AIC_SSCR AIC_SCCR 0xFFF8.212C AIC_EOSCR 0xFFF8.2130 W90N740CD/W90N740CDG R/W DESCRIPTION R/W Source Control Register 1 R/W Source Control Register 2 R/W Source Control Register 3 R/W Source Control Register 4 R/W Source Control Register 5 R/W Source Control Register 6 R/W Source Control Register 7 R/W ...
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... Interrupt sources with priority level 0 are promoted to FIQ. Interrupt sources with priority level other than 0 belong to IRQ. For interrupt sources of the same priority level, that located in the lower channel number has higher priority. W90N740CD/W90N740CDG R/W DESCRIPTION ...
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... IAS15 IAS14 IAS13 7 6 IAS7 IAS6 IAS5 This register indicates the status of each interrupt channel in consideration of the interrupt source type as defined in the corresponding Source Control Register, but regardless of its mask setting. W90N740CD/W90N740CDG R/W DESCRIPTION R Interrupt Raw Status Register RESERVED ...
Page 163
... ISx: Interrupt Status Indicates the status of corresponding interrupt channel 0 = Two possibilities: (1) The corresponding interrupt channel is inactive no matter whether it is enabled or disabled; ( active but not enabled 1 = Corresponding interrupt channel is both active and enabled (can assert an interrupt) W90N740CD/W90N740CDG R/W DESCRIPTION R Interrupt Status Register 29 28 ...
Page 164
... This register can help indexing into a branch table to quickly jump to the corresponding interrupt service routine. VECTOR [6:2]: Interrupt Vector interrupt occurs representing the interrupt channel that is active, enabled, and having the highest priority W90N740CD/W90N740CDG R/W DESCRIPTION R Interrupt Priority Encoding Register ...
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... This bit determines whether the corresponding interrupt channel is enabled or disabled. Every interrupt channel can be active no matter whether it is enabled or disabled interrupt channel is enabled, it does not definitely mean it is active. Every interrupt channel can be authorized by the AIC only when it is both active and enabled. W90N740CD/W90N740CDG R/W DESCRIPTION R ...
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... FIQ or IRQ. If both IRQ and FIQ are equal means there is no interrupt occurred. IRQ [1]: Interrupt Request 0 = nIRQ line is inactive nIRQ line is active. FIQ [0]: Fast Interrupt Request 0 = nFIQ line is inactive nFIQ line is active W90N740CD/W90N740CDG R/W DESCRIPTION R Output Interrupt Status Register 28 27 RESERVED ...
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... ADDRESS AIC_MDCR 0xFFF8.2124 RESERVED 15 14 MDC15 MDC14 MDC13 7 6 MDC7 MDC6 MDC5 MDC x: Mask Disable Command effect 1 = Disables the corresponding interrupt channel W90N740CD/W90N740CDG R/W DESCRIPTION Mask Enable Command Register RESERVED MEC12 MEC11 MEC4 ...
Page 168
... SSC13 7 6 SSC7 SSC7 SSC6 When the W90N740 is under debugging or verification, software can activate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SSCx: Source Set Command effect Activates the corresponding interrupt channel ...
Page 169
... When the W90N740 is under debugging or verification, software can deactivate any interrupt channel by setting the corresponding bit in this register. This feature is useful in hardware verification or software debugging. SCCx: Source Clear Command effect Deactivates the corresponding interrupt channels AIC End of Service Command Register (AIC_EOSCR) ...
Page 170
... GPIO3 GP2 GPIO2 GP1 GPIO1 GPIO0 GP0 Note: U means internal weak pull-up. 6.12.1 GPIO Controller Registers Map REGISTER ADDRESS GPIO_CFG 0xFFF8.3000 GPIO_DIR 0xFFF8.3004 GPIO_DATAOUT 0xFFF8.3008 GPIO_DATAIN 0xFFF8.300C DEBNCE_CTRL 0xFFF8.3010 W90N740CD/W90N740CDG MULTI-FUNCTION 1 TYPE NAME TYPE IO nIRQ3 IO nIRQ2 IO nIRQ1 IO nIRQ0 IO NXDREQ3 IO nXDACK IO TIMER1 IO TIMER0 ...
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... GPIOCFG18 [17:16]: Operating mode for GPIO18 11 GPIOCFG18 Name GPIO18 RESERVED OVRCUR is used as over current indicator if this field set to 10. nIRQ1 is one of the external interrupt input pins. GPIOCFG17 [15:14]: Operating mode for GPIO17 W90N740CD/W90N740CDG R/W DESCRIPTION R/W GPIO Configuration Register RESERVED 21 ...
Page 172
... GPIO13 STDBY is a USB IO port, which controls the external USB transceiver power-down mode. TIMER0 is the tone output of TIMER0. GPIOCFG12 [7:6]: Operating mode for GPIO12 11 GPIOCFG12 Name RESERVED GPIO12 nWDOG is the timeout output of Watch-Dog Timer. W90N740CD/W90N740CDG 10 Name Type Name RESERVED nIRQ0 10 Type Name ...
Page 173
... UART modem signal pins. GPIOCFG3_0 [1:0]: Operating mode for GPIO3, GPIO2, GPIO1, and GPIO0 11 GPIOCFG3_0 Name Type GPIO3 GPIO2 RESERVED GPIO1 GPIO0 GPIO Direction Register (GPIO_DIR) REGISTER ADDRESS 0xFFF8.3004 GPIO_DIR W90N740CD/W90N740CDG 11 10 Type Name Type O RESERVED O 10 Type Name Type Name nTOE O ...
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... GPIODO5 GPIODOx: GPIO output corresponding to bit x If the GPIOx is used as a general-purpose output pin, then the corresponding GPIODOx specifies the value to output from this pin. GPIO Data Input Register (GPIO_DATAIN) REGISTER ADDRESS GPIO_DATAIN 0xFFF8.3008 W90N740CD/W90N740CDG 28 27 RESERVED 20 19 GPIOD20 GPIOD19 12 11 ...
Page 175
... These three bits are used to select the clock rate for de-bouncer circuit. The relationship between the system clock HCLK and the de-bounce clock TCLK_BUN is as follows: DBE3 [3]: De-bouncer Circuit Enable for GPIO20 0 = De-bounce function is disabled 1 = De-bounce function is enabled W90N740CD/W90N740CDG 28 27 RESERVED 20 ...
Page 176
... DBE2 [2]: De-bouncer Circuit Enable for GPIO19 0 = De-bounce function is disabled 1 = De-bounce function is enabled DBE1 [1]: De-bouncer Circuit Enable for GPIO18 0 = De-bounce function is disabled 1 = De-bounce function is enabled DBE0 [0]: De-bouncer Circuit Enable for GPIO17 0 = De-bounce function is disabled 1 = De-bounce function is enabled W90N740CD/W90N740CDG Publication Release Date: September. 19, 2005 - 173 - Revision A7 ...
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... I IL Input Low Current I IHP Input High Current (pull-up) I ILP Input Low Current (pull-up) I IHD Input High Current (pull-down) I ILD Input Low Current (pull-down) W90N740CD/W90N740CDG CONDITION Depend on driving Depend on driving F cpu = 80MHz F cpu = 80MHz ...
Page 178
... T Output 1.5V Delay SYM. D [31:0] Setup Time T DSU D [31:0] Hold Time [31:0], A [24:0], nSCS [1:0], SDQM [3:0], CKE, nSWE, nSRAS, nSCAS T DO W90N740CD/W90N740CDG CONDITIONS ⎜DP − DM⎥ INPUT Includes 1.5 KΩ KΩ Steady state drive 1.5V T DSU Input Valid DO Output Valid PARAMETER Publication Release Date: September ...
Page 179
... EMREQ Setup Time EMSU T EMREQ Hold Time EMH T EMACK Output Delay Time EMAO 7.3.3 EBI/(ROM/SRAM/External I/O) AC Characteristics MCLK T NECSO nECS[3:0] T ADDO A[24:0] nOE D[31:0] nWAIT nWBE[3:0] D[31:0] W90N740CD/W90N740CDG EMSU T EMH T EMAO DESCRIPTION Address Valid T NOEO NWASU NWAH T NWBO T DO Write Data Vaild - 176 - T EMAO MIN ...
Page 180
... SYM. DESCRIPTION T Rise Time (Full Speed Fall Time (Full Speed F T Rise/Fall Time Matching (Full Speed) RFM T Full Speed Data Rate DRATE W90N740CD/W90N740CDG DESCRIPTION Rise Tim e 90% Differential Data Lines 10 50pF Low Speed: 75ns 50pF, 300ns Data Signal Rise and Fall Time ...
Page 181
... RX_D [3:0] RX_DV RX_ERR SYMBOL DESCRIPTION T Transmit Output Delay Time TXO T Receive Setup Time RXSU Receive Hold Time T RXH MDC MDIO W90N740CD/W90N740CDG T TXO Valid Transmit Signal Timing Relationships at MII T RXSU VALID INPUT Receive Signal Timing Relationships at MII T T MDSU MDH VALID INPUT ...
Page 182
... SYMBOL DESCRIPTION T MDIO Output Delay Time MDO T MDIO Setup Time MDSU T MDIO Hold Time MDH W90N740CD/W90N740CDG lid MDIO Write to PHY Timing MIN Publication Release Date: September. 19, 2005 - 179 - MAX. UNIT Revision A7 ...
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... PACKAGE DIMENSIONS 176-Pin LQFP (note that the value in inches may have some inaccuracy translated from the value in millimeter) W90N740CD/W90N740CDG - 180 - ...
Page 184
... W90N740 REGISTERS MAPPING TABLE R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written System Manager Control Registers Map REGISTER ADDRESS PDID 0xFFF0.0000 ARBCON 0xFFF0.0004 PLLCON 0xFFF0.0008 CLKSEL 0xFFF0.000C EBI Control Registers Map REGISTER ADDRESS EBICON 0xFFF0.1000 ROMCON 0xFFF0.1004 SDCONF0 0xFFF0 ...
Page 185
... CAM11L_0 0xFFF0.305C CAM12M_0 0xFFF0.3060 CAM12L_0 0xFFF0.3064 CAM13M_0 0xFFF0.3068 CAM13L_0 0xFFF0.306C CAM14M_0 0xFFF0.3070 CAM14L_0 0xFFF0.3074 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM Command Register R/W CAM enable register R/W CAM1 Most Significant Word Register R/W CAM1 Least Significant Word Register R/W CAM2 Most Significant Word Register R/W CAM2 Least Significant Word Register ...
Page 186
... TXDLSA_0 0xFFF0.309C RXDLSA_0 0xFFF0.30A0 DMARFC_0 0xFFF0.30A4 TSDR_0 0xFFF0.30A8 RSDR_0 0xFFF0.30AC FIFOTHD_0 0xFFF0.30B0 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM15 Most Significant Word Register R/W CAM15 Least Significant Word Register R/W CAM16 Most Significant Word Register R/W CAM16 Least Significant Word Register R/W MAC Interrupt Enable Register R/W MAC Command Register ...
Page 187
... DMA REGISTERS DMARFS_0 0xFFF0.30C8 R/W DMA Receive Frame Status Register CTXDSA_0 0xFFF0.30CC CTXBSA_0 0xFFF0.30D0 CRXDSA_0 0xFFF0.30D4 CRXBSA_0 0xFFF0.30D8 W90N740CD/W90N740CDG R/W DESCRIPTION R MAC Receive Pause count register R MAC Receive Pause Current Count Register R MAC Remote pause count register Current Transmit Descriptor Start Address ...
Page 188
... CAM10L_1 0xFFF0.3854 CAM11M_1 0xFFF0.3858 CAM11L_1 0xFFF0.385C CAM12M_1 0xFFF0.3860 CAM12L_1 0xFFF0.3864 CAM13M_1 0xFFF0.3868 CAM13L_1 0xFFF0.386C W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM Command Register R/W CAM enable register R/W CAM1 Most Significant Word Register R/W CAM1 Least Significant Word Register R/W CAM2 Most Significant Word Register R/W CAM2 Least Significant Word Register ...
Page 189
... DMA REGISTERS TXDLSA_1 0xFFF0.389C RXDLSA_1 0xFFF0.38A0 DMARFC_1 0xFFF0.38A4 TSDR_1 0xFFF0.38A8 RSDR_1 0xFFF0.38AC FIFOTHD_1 0xFFF0.38B0 W90N740CD/W90N740CDG R/W DESCRIPTION R/W CAM14 Most Significant Word Register R/W CAM14 Least Significant Word Register R/W CAM15 Most Significant Word Register R/W CAM15 Least Significant Word Register R/W CAM16 Most Significant Word Register ...
Page 190
... R/W GDMA_DSTB1 0xFFF0.4028 R/W GDMA_TCNT1 0xFFF0.402C R/W GDMA_CSRC1 0xFFF0.4030 GDMA_CDST1 0xFFF0.4034 GDMA_CTCNT1 0xFFF0.4038 W90N740CD/W90N740CDG R/W DESCRIPTION R/W MAC Interrupt Status Register R/W MAC General Status Register R MAC Receive Pause count register R MAC Receive Pause Current Count Register R MAC Remote pause count register R/W DMA Receive Frame Status Register ...
Page 191
... HcRhDescriptorA 0xFFF0.5048 HcRhDescriptorB 0xFFF0.504C HcRhStatus 0xFFF0.5050 HcRhPortStatus [1] 0xFFF0.5054 HcRhPortStatus [2] 0xFFF0.5058 W90N740CD/W90N740CDG R/W DESCRIPTION R Host Controller Revision Register R/W Host Controller Control Register R/W Host Controller Command Status Register R/W Host Controller Interrupt Status Register R/W Host Controller Interrupt Enable Register R/W Host Controller Interrupt Disable Register Host Controller Communication Area ...
Page 192
... NATCFG63 0xFFF0.61FC R/W NAT Entry 63 Configuration Register EXMACM 0xFFF0.6200 EXMACL 0xFFF0.6204 INMACM 0xFFF0.6208 INMACL 0xFFF0.620C R/W W90N740CD/W90N740CDG R/W DESCRIPTION R/W NAT Command Register W NAT Counter 0 Clear Register W NAT Counter 1 Clear Register W NAT Counter 2 Clear Register W NAT Counter 3 Clear Register R/W NAT Entry 0 Configuration Register R/W NAT Entry 1 Configuration Register ...
Page 193
... LSPN63 0xFFF0.6FEC LSMAC63M 0xFFF0.6FF0 LSMAC63L 0xFFF0.6FF4 RSMAC63M 0xFFF0.6FF8 RSMAC63L 0xFFF0.6FFC W90N740CD/W90N740CDG R/W DESCRIPTION R/W NAT Masquerading IP Address Entry 0 R/W NAT Masquerading Port Number Entry 0 R/W Local Station IP Address Entry 0 R/W Local Station Port Number Entry 0 Local Station MAC Address Most Significant R/W Word Register for Entry 0 Local Station MAC Address Least Significant ...
Page 194
... GPIO Controller Registers Map REGISTER ADDRESS GPIO_CFG 0xFFF8.3000 GPIO_DIR 0xFFF8.3004 GPIO_DATAOUT 0xFFF8.3008 GPIO_DATAIN 0xFFF8.300C DEBNCE_CTRL 0xFFF8.3010 W90N740CD/W90N740CDG DESCRIPTION R Receive Buffer Register (DLAB = 0) W Transmit Holding Register (DLAB = 0) Interrupt Enable Register (DLAB = 0) Divisor Latch Register (LS) (DLAB = 1) Divisor Latch Register (MS) (DLAB = 1) R Interrupt Identification Register ...
Page 195
... AIC_IPER 0xFFF8.210C AIC_ISNR 0xFFF8.2110 AIC_IMR 0xFFF8.2114 AIC_OISR 0xFFF8.2118 AIC_MECR 0xFFF8.2120 AIC_MDCR 0xFFF8.2124 AIC_SSCR 0xFFF8.2128 AIC_SCCR 0xFFF8.212C AIC_EOSCR 0xFFF8.2130 W90N740CD/W90N740CDG R/W DESCRIPTION R/W Source Control Register 1 R/W Source Control Register 2 R/W Source Control Register 3 R/W Source Control Register 4 R/W Source Control Register 5 R/W Source Control Register 6 R/W Source Control Register 7 R/W ...
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... A2 May 27, 2003 A3 Sep. 3, 2004 A4 Nov. 26, 2004 A5 April 19, 2005 A6 Aug. 18, 2005 A7 Sep. 19, 2006 W90N740CD/W90N740CDG PACKAGE DESCRIPTION 176 Leads, body 1.4 mm 176 Leads, body 1.4 mm, Lead free package PAGE - Initial Issued - Add DC specifications in 8.2 Change Pin Description Page 54 Change tCOH description Page 56 Remove Fig ...
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... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W90N740CD/W90N740CDG Important Notice - 194 - ...