TSC2302

Manufacturer Part NumberTSC2302
DescriptionSmart 4-wire Touch Screen Controller With Stereo Codec With Hp Amplifier
ManufacturerTexas Instruments Incorporated
TSC2302 datasheet
 


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PROGRAMMABLE TOUCH SCREEN CONTROLLER
FEATURES
SPI™ Serial Interface
Touch Screen Controller
– 4-Wire Touch Screen Interface
– Internal Detection of Screen Touch
– Touch Pressure Measurement
– Ratiometric Conversion
– Programmable 8-, 10- or 12-Bit Resolution
– Programmable Sampling Rates Up to
125 kHz
– Direct Battery Measurement (0 to 6 V)
– On-Chip Temperature Measurement
– Integrated Touch Screen Processor
Reduces Host CPU Interrupts and Overhead
– Internal Timing Control With Programmable
Delays and Averaging
Stereo Audio Codec
– 20-Bit Delta-Sigma ADC/DAC
– Dynamic Range: 98 dB
– Sampling Rate Up to 48 kHz
2
– I
S Serial Interface
– Stereo 16-Ω Headphone Driver
Full Power-Down Control
8-Bit Current Output DAC
On-Chip Crystal Oscillator
Programmable Bass/ Midrange/ Treble EQ
Effects Processing
Single 2.7-V to 3.6-V Supply
48-pin QFN Package
SPI is a trademark of Motorola.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
clude testing of all parameters.
WITH STEREO AUDIO CODEC
APPLICATIONS
Personal Digital Assistants
Cellular Phones
MP3 Players
Internet Appliances
Smartphones
DESCRIPTION
The TSC2302 is a highly integrated PDA analog
interface circuit. It contains a complete 12-bit A/D
resistive touch screen converter (ADC) including
drivers, touch pressure measurement capability, and
8-bit D/A converter (DAC) output for LCD contrast
control. The TSC2302 offers programmable resolution
of 8, 10, and 12 bits and sampling rates up to 125 kHz
to accommodate different screen sizes. The TSC2302
interfaces to the host controller through a standard SPI
serial interface.
The TSC2302 features a high-performance 20-bit,
48-ksps stereo audio codec with highly integrated
analog functionality. The audio portion of the TSC2302
contains microphone input with built-in pre-amp and
microphone bias circuit, an auxiliary stereo analog
input, a mono line-level output, and a stereo
headphone amplifier output. The digital audio data is
transferred through a standard I
programmable PLL for generating audio clocks from a
wide variety of system clocks is also included.
The TSC2302 also offers two battery measurement
inputs capable of battery voltages up to 6 V, while
operating at a supply voltage of only 2.7 V. It also has
an on-chip temperature sensor capable of reading
0.3°C resolution. The TSC2302 is available in a
48-lead QFN.
US Patent No. 6246394
TSC2302
SLAS394 – JULY 2003
2
S interface. A fully
Copyright © 2003, Texas Instruments Incorporated

TSC2302 Summary of contents

  • Page 1

    ... SPI serial interface. The TSC2302 features a high-performance 20-bit, 48-ksps stereo audio codec with highly integrated analog functionality. The audio portion of the TSC2302 contains microphone input with built-in pre-amp and microphone bias circuit, an auxiliary stereo analog input, a mono line-level output, and a stereo headphone amplifier output ...

  • Page 2

    ... TSC2302 SLAS394 – JULY 2003 AVDD−1V AVDD 30 k VCM 20 k AGND Mute, 0db, 6dB, 12dB MICIN RLINEIN +12dB to − 35dB 0.5dB steps LLINEIN MONO+ VREF+ VREF− Headphone Driver HPR HPVDD HPGND HPL Headphone Driver DACSET DACOUT VREFIN X+ Touch X− ...

  • Page 3

    ... TSC2302 SLAS394 – JULY 2003 ORDERING TRANSPORT MEDIA NUMBER QUANTITY TSC2302IRGZ Trays, 308 TSC2302IRGZR Tape and reel, 2000 TSC2302 4 V ±0 ( ( -40°C to 125°C -55°C to 150°C 150°C 260° ...

  • Page 4

    ... Line, Mic inputs HP outputs ADC performance measured using kHz No input 1 kHz, -0.5 dB input DAC performance measured at HP Outputs using kHz DAC playback through headphone driver Ω Ω www.ti.com TSC2302 UNITS MIN TYP MAX 0 +VREFIN V ρ µ ...

  • Page 5

    ... TTL loads OL 1-kHz SAR sample rate, external V ref 20-kHz SAR sample rate, internal V ref 44.1-kHz Playback 2.7V DD Mono 8-kHz record 2.7V DD Audio fully powered down www.ti.com TSC2302 SLAS394 – JULY 2003 TSC2302 UNITS MIN TYP MAX -83 -70 dB -77 dB 0.75 1 ...

  • Page 6

    ... TSC2302 SLAS394 – JULY 2003 AUX1 HPVDD HPGND AVDD AGND MONO+ NC PIN I/O NAME VBAT1 3 I VBAT2 4 I/O VREFIN PENIRQ I/O GPIO_5/CLKO DGND LRCLK 22 I I2SDIN 23 O I2SDOUT ...

  • Page 7

    ... X- position input Y- position input X+ position input Y+ position input Analog supply for headphone amplifier and touch screen circuitry SAR auxiliary analog input 1 TIMING DIAGRAM BIT . . . 1 LSB OUT BIT . . . 1 LSB IN www.ti.com TSC2302 SLAS394 – JULY 2003 dis 7 ...

  • Page 8

    ... TSC2302 SLAS394 – JULY 2003 TIMING CHARACTERISTICS (1) (2) All specifications typical at -40°C to +85°C, +V PARAMETER SCLK period Enable lead time Enable lag time Sequential transfer delay Data setup time Data hold time (inputs) Data hold time (outputs) Slave access time ...

  • Page 9

    ... Temperature (5C) Figure 5. DAC OUTPUT CURRENT vs TEMPERATURE 1.2 1.15 1.1 1.05 1 0.95 0.9 – 100 Temperature (C) Figure 8. www.ti.com TSC2302 SLAS394 – JULY 2003 CONVERSION SUPPLY CURRENT vs TEMPERATURE 2 1.95 1.9 1.85 1.8 1.75 1.7 1.65 1.6 – 100 Temperature (5C) Figure 3. INTERNAL OSCILLATOR FREQUENCY vs TEMPERATURE 9.1 9 8.9 8.8 osc 8 ...

  • Page 10

    ... TSC2302 SLAS394 – JULY 2003 TYPICAL CHARACTERISTICS (continued +25° REF TEMP1 DIODE VOLTAGE vs TEMPERATURE 750 700 650 600 550 500 450 400 – Temperature (5C) Figure 10. SNR OF ADC (LINEIN) vs TEMPERATURE –60 –40 –20 ...

  • Page 11

    ... Vdd (V) Figure 23. DAC MAXIMUM CURRENT vs SUPPLY VOLTAGE 1.0899 1.0878 1.0857 1.0836 2.5 3 3.5 Vdd (V) Figure 26. www.ti.com TSC2302 SLAS394 – JULY 2003 2.5-V INTERNAL REFERENCE vs SUPPLY VOLTAGE 2.4875 2.48675 2.486 2.48525 2.4845 2.48375 2.483 2.5 3 3.5 Vdd (V) Figure 21. TEMP1 DIODE VOLTAGE vs SUPPLY VOLTAGE 611 610 ...

  • Page 12

    ... TSC2302 SLAS394 – JULY 2003 TYPICAL CHARACTERISTICS (continued +25° REF INL MAXIMUM vs SUPPLY VOLTAGE 4.5 4.25 4 3.75 3.5 3.25 3 2.5 3 3.5 Vdd (V) Figure 28. MICBIAS vs SUPPLY VOLTAGE 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 1.7 1.6 1.5 2.5 3 3.5 Vdd (V) Figure 31. THD OF DAC (HP DRIVER) vs SUPPLY VOLTAGE –78 –79 –80 –81 –82 –83 –84 –85 2.5 3 3.5 Vdd (V) Figure 34 ...

  • Page 13

    ... Registers control the operation of the touch screen A/D converter, and audio codec. The result of measurements made are placed in the TSC2302 memory map and can be read by the host at any time. Three signals are available from the TSC2302 to indicate that data is available for the host to read. The DAV output indicates that an analog-to-digital conversion has completed and that data is available ...

  • Page 14

    ... X+ input to the ADC input, driving Y+ to +VDD and Y- to GND using switches internal to the TSC2302, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect the conversion, due to the high input impedance of the ADC ...

  • Page 15

    ... PENIRQ signal; or conversion completely controlled by the host processor. A/D CONVERTER The analog inputs of the TSC2302 are shown in Figure 42. The analog inputs (X, Y, and Z touch panel coordinates, battery voltage monitors, chip temperature, and auxiliary inputs) are provided via a multiplexer to the successive approximation register (SAR) analog-to-digital converter (ADC). The A/D architecture is based on capacitive redistribution architecture, which inherently includes a sample/hold function ...

  • Page 16

    ... Figure 42. Simplified Diagram of the Touch Screen Analog Input Section Data Format The TSC2302 output data is in straight binary format as shown in Figure 43. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. ...

  • Page 17

    ... Reference The TSC2302 has an internal voltage reference that can be set to 1 2.5 V, through the reference control register. This reference can also be set to automatically power down between conversions to save power, or remain on to reduce settling time. The internal reference voltage is only used in the single-ended mode for battery monitoring, temperature measurement, and for utilizing the auxiliary inputs ...

  • Page 18

    ... Y– Figure 44. PENIRQ Functional Block Diagram In modes where the TSC2302 needs to detect if the screen is still touched (for example, when doing a PENIRQ-initiated X, Y, and Z conversion), the TSC2302 must reconnect the drivers so that the 50-kΩ resistor is connected again. Because of the high value of this pullup resistor, any capacitance on the touch screen inputs cause a long delay time, and may prevent the detection from occurring correctly ...

  • Page 19

    ... MISO pin to the master shift register. When the POL pin of the TSC2302 is tied high (POL=1), the idle state of the serial clock for the TSC2302 is low, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). When the POL pin of the TSC2302 is tied low (POL=0), the idle state of the serial clock is high, which corresponds to a clock polarity setting of 1 (typical microprocessor SPI control bit CPOL = 1) ...

  • Page 20

    ... The processor can then start clocking data out of the TSC2302. The TSC2302 automatically increments its address pointer to the end of the page; if the host processor continues clocking data out past the end of a page, the TSC2302 simply sends back the value 0xFFFF ...

  • Page 21

    ... The TSC2302 has several 16-bit registers that allow control of the device as well as providing a location for results from the TSC2302 to be stored until read by the host microprocessor. These registers are separated into three pages of memory in the TSC2302: a data page (Page 0), a control page (Page 1), and an audio control page (Page 2). The memory map is shown in Table 2. ...

  • Page 22

    ... Table 3. Register Summary for TSC2302 D13 D12 D11 D10 R11 R10 R11 R10 R11 R10 ...

  • Page 23

    ... Register Summary for TSC2302 (continued) PAGE ADDR REGISTER D15 D14 D13 (HEX) NAME 1 0F reserved reserved reserved reserved reserved reserved reserved reserved reserved ...

  • Page 24

    ... Pen Status/Control Mode. Reading this bit allows the host to determine if the screen is touched. Writing to this bit determines the mode used to read coordinates: host controlled or under control of the TSC2302 responding to a screen touch. When reading, the PENSTS bit indicates if the pen is down or not. When writing to this register, this bit determines if the TSC2302 controls the reading of coordinates the coordinate conversions are host-controlled ...

  • Page 25

    ... Table 5. STS Bit Operation STS DESCRIPTION 0 Converter is busy 1 Converter is not busy (default) 0 Normal operation 1 Stop conversion and power down Table 6. ADC Function Select FUNCTION Table 7. ADC Resolution Control FUNCTION www.ti.com TSC2302 SLAS394 – JULY 2003 25 ...

  • Page 26

    ... TSC2302 SLAS394 – JULY 2003 Bits[7:6] — AV1, AV0 Converter Averaging Control. These two bits (see Table 8) allow you to specify the number of averages the converter performs. Note that when averaging is used, the STS/STP bit and the DAV output indicates that the converter is busy until all conversions necessary for the averaging are complete ...

  • Page 27

    ... X Bit 4 —INT Internal Reference Mode. If this bit is written the TSC2302 uses its internal reference; if this bit the part assumes an external reference is being supplied. The default state for this bit is to select an external reference (0). This bit is the same whether reading or writing. ...

  • Page 28

    ... TSC2302 SLAS394 – JULY 2003 Bits [3:2] — DL1, DL0 Reference Power-Up Delay. When the internal reference is powered up, a finite amount of time is required for the reference to settle. If measurements are made before the reference has settled, these measurements are in error. These bits allow for a delay time for measurements to be made after the reference powers up, thereby assuring that the reference has settled ...

  • Page 29

    ... Bits [2:0] — SNS[2:0] Sense time selection bits. These bits set the amount of time the TSC2302 waits to sense a screen touch between coordinate axis conversions in self-controlled mode. SNS2 SNS1 ...

  • Page 30

    ... SPI interface to see whether data is available, without dedicating a GPIO pin from the host processor to the TSC2302 DAV pin. This bit is normally high, goes low when touch screen or keypad data is available, and is reset high when all the new data has been read. When written to, this bit becomes KBC1, operation detailed below ...

  • Page 31

    ... When using a nonaudio standard MCLK frequency or crystal that is not covered by any of the automatic PLL settings in MCLK[1:0], the user must manually configure the TSC2302 PLL to generate the proper clock for the audio data converters. The proper clock for any sampling rates that are submultiples of 44.1 kHz is 512 x 44.1 kHz = 22 ...

  • Page 32

    ... SLAS394 – JULY 2003 TSC2302 DATA REGISTERS The data registers of the TSC2302 hold data results from conversions or keypad scans, or the value of the DAC output current. All of these registers default to 0000H upon reset, except the DAC register, which is set to 0080H, representing the midscale output of the DAC. ...

  • Page 33

    ... OPERATION - TOUCH SCREEN MEASUREMENTS Conversion Controlled by TSC2302 Initiated at Touch Detect In this mode, the TSC2302 detects when the touch panel is touched and causes the PENIRQ line to go low. At the same time, the TSC2302 powers up its internal clock. It then turns on the Y-drivers, and after a programmed panel voltage stabilization time, powers up the ADC and convert the Y coordinate. If averaging is selected, several conversions may take place ...

  • Page 34

    ... TSC2302 SLAS394 – JULY 2003 TOUCH SCREEN SCAN X AND Y PENIRQ INITIATED Screen Touch Issue Interrupt PENIRQ Is PENSTS =1 Y Start Clock Turn On Drivers: Y Panel Voltage Stabilization Done Y Power up ADC Convert Y coordinates Is Data N Averaging Done Y Store Y Coordinates in Y Register Power Down ADC ...

  • Page 35

    ... Averaging Done Y Store X Coordinates in X Register Power Down ADC Turn off clock Is Screen Touched Reset PENIRQ and Scan Trigger Done Y www.ti.com TSC2302 SLAS394 – JULY 2003 Turn On Drivers: Y Panel Voltage Stabilization Done Y Power up ADC Convert Z1 coordinates Is Data N Averaging ...

  • Page 36

    ... In this mode, the TSC2302 detects when the touch panel is touched and causes the PENIRQ line to go low. The host recognizes the interrupt request, and then writes to the ADC control register to select one of the touch screen scan functions (single X-, Y-, or Z-conversions, continuous X/Y or X/Y/Z1/Z2 Conversions) ...

  • Page 37

    ... Figure 48. X and Y Coordinate Touch Screen Scan, Initiated by Host Go To Host Controlled Conversion Done Turn off clock Reset PENIRQ and Scan Trigger Done www.ti.com TSC2302 SLAS394 – JULY 2003 Turn On Drivers: X Panel Voltage Stabilization Done Y Power up ADC Convert X coordinates Is Data Averaging Done Y ...

  • Page 38

    ... TSC2302 SLAS394 – JULY 2003 TOUCH SCREEN SCAN X, Y AND Z HOST INITIATED Screen Touch Issue Interrupt PENIRQ Host Controlled Is PENSTS =1 Conversion Host Writes A/D Converter Done Control Register Reset PENIRQ Start Clock Turn On Drivers: Y Panel Voltage Stabilization Done Y Power up ADC ...

  • Page 39

    ... Figure 50. X Coordinate Reading Initiated by Host Go To Host Controlled Conversion Done Start Clock Turn On Drivers: X Panel Voltage Stabilization Done Y www.ti.com TSC2302 SLAS394 – JULY 2003 Convert X coordinates Is Data N Averaging Done Y Store X Coordinates in X Register Power Down ADC Set /DAV = 0 ...

  • Page 40

    ... TSC2302 SLAS394 – JULY 2003 TOUCH SCREEN SCAN Y COORDINATE HOST INITIATED Screen Touch Issue Interrupt PENIRQ Is PENSTS =1 Host Writes A/D Converter Control Register Reset PENIRQ Are Drivers On Y Start Clock Power up ADC Convert Y coordinates N Is Data Averaging Done Figure 51. Y Coordinate Reading Initiated by Host ...

  • Page 41

    ... Figure 52. Z Coordinate Reading Initiated by Host Go To Host Controlled Conversion DONE Start Clock Turn On Drivers: Y Panel N Voltage Stabilization Done Y www.ti.com TSC2302 SLAS394 – JULY 2003 Convert Z2 coordinates Is Data N Averaging Done Y Store Z2 Coordinates in Z2 Register Power Down ADC Set /DAV = 0 Turn off clock ...

  • Page 42

    ... SLAS394 – JULY 2003 Conversion Controlled by the Host In this mode, the TSC2302 detects when the touch panel is touched and causes the PENIRQ line to go low. The host recognizes the interrupt request. Instead of starting a sequence in the TSC2302, which then reads each coordinate in turn, the host now must control all aspects of the conversion. An example sequence would be: (a) PENIRQ goes low when screen is touched ...

  • Page 43

    ... Turn On Drivers: X Done Figure 53. X Coordinate Reading Controlled by Host Start Clock N Turn On Drivers: X Panel Voltage Y Stabilization Done N N www.ti.com TSC2302 SLAS394 – JULY 2003 Host Writes A/D Converter Control Register Are Drivers On Y Start Clock Power up ADC Convert X coordinates Is Data Averaging ...

  • Page 44

    ... TSC2302 SLAS394 – JULY 2003 Screen Touch Issue Interrupt PENIRQ Go To Host Controlled N Is PENSTS =1 Host Writes A/D Converter Control Register Reset PENIRQ Turn On Drivers: Y Done Figure 54. Y Coordinate Reading Controlled by Host 44 HOST CONTROLLED Y COORDINATE Start Clock Turn On Drivers: Y Conversion ...

  • Page 45

    ... Figure 55. Z Coordinate Reading Controlled by Host Go To Host Controlled Conversion DONE N Start Clock Turn On Drivers: Y Panel Voltage Stabilization Done Y www.ti.com TSC2302 SLAS394 – JULY 2003 Convert Z2 coordinates Is Data Averaging Done Y Store Z2 Coordinates in Z2 Register Power Down ADC Set /DAV = 0 N ...

  • Page 46

    ... During the final test of the end product, the diode voltage would be measured by the TSC2302 ADC at a known room temperature, and the corresponding digital code stored in system memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3° ...

  • Page 47

    ... Power up ADC Convert Temperature Input Data Averaging Store Temperature Input 1 in TEMP1 Register Figure 57. Single Temperature Measurement Mode TEMPERATURE INPUT 1 Power Down ADC Power Down Set /DAV = 0 Turn off clock Done Y www.ti.com TSC2302 SLAS394 – JULY 2003 Reference DONE 47 ...

  • Page 48

    ... TSC2302. An example of this is shown in Figure 59, where a battery voltage ranging may be regulated by a dc/dc converter or low-dropout regulator to provide a lower supply voltage to the TSC2302. The battery voltage can vary from 0 while maintaining the voltage to the TSC2302 at a level of 2.7 V-3.6 V. The input voltage ...

  • Page 49

    ... N coordinate REF where t is the reference delay time as given in Table 13. REF 2.7 V DC/DC Converter + V CC 0.125 BAT1 7.5 kW 2.5 kW 2.7 V DC/DC Converter + V CC 0.125 BAT2 5 4.4 ms AVG BITS conv www.ti.com TSC2302 SLAS394 – JULY 2003 ADC ADC = 2.5 V REF (10) 49 ...

  • Page 50

    ... TSC2302 SLAS394 – JULY 2003 N This assumes the reference control register is configured to power up the internal reference when needed. 50 BATTERY INPUT 1 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Delay) Power up ADC Convert Battery Input 1 Is Data Averagin Done Y Store Battery Input 1 in BAT1 Register Figure 60 ...

  • Page 51

    ... Power up ADC Convert Battery Input Set /DAV = 0 2 Turn off clock Is Data Averaging Done Y Store Battery Input 2 in BAT2 Register Figure 61. V Measurement Process BAT2 . Figure 62 and Figure 63 illustrate the process. Applications REF www.ti.com TSC2302 SLAS394 – JULY 2003 Reference DONE 51 ...

  • Page 52

    ... TSC2302 SLAS394 – JULY 2003 52 AUXILIARY INPUT 1 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Delay) Power up ADC Convert Auxiliary Input 1 Is Data N Averaging Done Y Store Auxiliary Input 1 in AUX1 Register Figure 62. AUX1 Measurement Process Power Down ADC Power Down ...

  • Page 53

    ... Power up ADC Convert Auxiliary N Store Auxiliary Input 2 in AUX2 Register Figure 63. AUX2 Measurement Process AUXILIARY INPUT 2 Register Power Down ADC Power Down Reference Input 2 Set /DAV = 0 Is Data Averaging Turn off clock Done Y DONE www.ti.com TSC2302 SLAS394 – JULY 2003 53 ...

  • Page 54

    ... DAV pin is asserted low, signaling the host to read the data. Thus, with one write to the TSC2302, the host can cause four different measurements to be made. Because the battery and auxiliary data registers are consecutive in memory, all four registers can be read in one SPI transaction, as described in Figure 45 ...

  • Page 55

    ... LCD contrast control bias. V+ can be a higher voltage than the supply voltage for the TSC2302. The only restriction is that the voltage on the AOUT pin can never go above the absolute maximum ratings for the device, and should stay above 1.5 V for linear operation. ...

  • Page 56

    ... Figure 66. DAC Output Current Range vs RRNG Resistor Value For example, consider an LCD that has a contrast control voltage VBIAS that can range from that draws 400 µA when used, and has an available 5-V supply. This is higher than the TSC2302 supply voltage, but it is within the absolute maximum ratings. ...

  • Page 57

    ... Figure 67. DAC Circuit When Using V+ Higher Than BIAS R2 2N3904 AOUT VDD DAC ARNG RRNG www.ti.com TSC2302 SLAS394 – JULY 2003 . supply 57 ...

  • Page 58

    ... I2SDOUT (pin 27). For the TSC2302, these formats are selected through the I2SFM bits in Reg 00h The following figures illustrate audio data input/output formats and timing. The TSC2302 can accept 32-, 48-, or 64-bit clocks (BCKIN) in one clock of LRCIN. Only 16-bit data formats can be selected when 32-bit clocks/LRCIN are applied. ...

  • Page 59

    ... LSB MSB L– LSB MSB L– LSB MSB www.ti.com TSC2302 SLAS394 – JULY 2003 R– MSB LSB R– LSB R– LSB R– LSB R– ...

  • Page 60

    ... TSC2302 SLAS394 – JULY 2003 – – LRCIN BCKIN I2SDIN – – LRCIN BCKIN I2SDOUT LRCIN ...

  • Page 61

    ... Falling time to all signals Audio Data Converters The TSC2302 includes a stereo 20-bit audio DAC and a stereo 20-bit audio ADC. The DAC and ADC are both capable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz kHz. The DAC and ADC must operate at the same sampling rate. ...

  • Page 62

    ... TSC2302 SLAS394 – JULY 2003 Because of this soft-stepping, the host does not know whether the DAC has actually been fully muted or not. This may be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the part provides a flag back to the host via a read-only SPI register bit (Bit 0, Reg 04h that alerts the host when the part has completed the soft-stepping, and the actual volume has reached the desired volume level ...

  • Page 63

    ... This transfer function(s) can be determined by the user and loaded to the TSC2302 at power-up, and the feature can then be switched on or off by the user during normal operation filter with gain over designed and used, and large-scale signals are played at high amplitude through the DAC, overloading and undesirable effects can occur ...

  • Page 64

    ... Monophonic Output (MONO) The mono output of the TSC2302 can be used to drive a power amplifier which drives a low-impedance speaker. This block can output either a mono mix of the stereo outputs, or the analog input to the left-channel ADC. This is selected through the MONS bit (Bit 2, Reg 04h ...

  • Page 65

    ... Power Consumption The TSC2302 provides maximum flexibility to the user for control of power consumption. Towards that end, every section of the TSC2302 audio codec can be independently powered down. The power down status of the different sections is controlled by Reg 05h The analog bypass path, headphone amplifier, mono output, stereo DAC, left channel ADC, right channel ADC, microphone bias, crystal oscillator, and oscillator clock buffer sections can all be powered down independently ...

  • Page 66

    ... TSC2302 SLAS394 – JULY 2003 Bits [15:14] — HPF1-HPF0 ADC High Pass Filter. These two bits select the pass-band for the high-pass filter or disable the filter. The default state of the filter is enabled, with -3-dB frequency at 0.000019xFs. HPF1 HPF0 DESCRIPTION 0 0 HPF Disabled, signal passes through unaltered ...

  • Page 67

    ... MCLK[1:0] 2 Table 30 Sample Rate Select I2SFS1 I2SFS0 FUNCTION kHz (default 44.1 kHz kHz kHz 22.05 kHz kHz kHz 11.05 kHz kHz www.ti.com TSC2302 SLAS394 – JULY 2003 67 ...

  • Page 68

    ... The ADC volume control register controls the independent programmable gain amplifiers (PGA’s) on the left and right channel inputs to the audio ADCs of the TSC2302. The gain of these PGAs can be adjusted from - + 0.5-dB steps. The ADC inputs can also be hard-muted, or internally shorted to VCM so that no input signal is seen ...

  • Page 69

    ... The DAC volume control register controls the independent digital gain controls on the left and right channel audio DAC’s of the TSC2302. The gain of the DACs can be adjusted from -63 0.5-dB steps. The DAC inputs can also be muted, so that all zeroes are sent to the DAC interpolation filters. ...

  • Page 70

    ... A/D or D/A conversion. This feature can be used for playback of an external analog source, such stereo tuner through the TSC2302’s headphone amplifier. The gain of these PGA’s can be adjusted from -35 0.5 dB steps. The bypass paths can also be muted, so that no signal is transmitted ...

  • Page 71

    ... BPVR[6:0] = 0100000 (032d) = -35.5 dB (Min) BPVR[6:0] = 0d-31d = mute AUDIO CONTROL REGISTER 2 (Page 2, Address 04H) The Audio Control Register 2 of the TSC2302 controls the input to the mono output, and the soft-stepping function of the TSC2302 volume controls. The keyclick control register is formatted as follows: Bit 15 ...

  • Page 72

    ... The audio power / miscellaneous control register of the TSC2302 controls the powering down of various audio blocks of the TSC2302. The default state of the TSC2302 has all audio blocks powered down. Before using any of the audio blocks, they must be powered up by writing to this register. This register also controls the crystal oscillator clock and buffer, the bass-boost filter, and the de-emphasis filter ...

  • Page 73

    ... Microphone Bias Power Down. This is used to power up (set power down (set to 1) the microphone bias output. Table 42. Microphone Bias Power Down OSCC DESCRIPTION 0 Microphone bias is on. 1 Microphone bias is off (default). Table 41. Power Up/Down Flag www.ti.com TSC2302 SLAS394 – JULY 2003 73 ...

  • Page 74

    ... TSC2302 SLAS394 – JULY 2003 Bit 5 — OSCC Crystal Oscillator Control. This bit turns ON/OFF the crystal Oscillator. OSCC DESCRIPTION 0 Crystal oscillator is off (default). 1 Crystal oscillator is on. Bit 4 — BCKC Oscillator Clock Buffer Control. This bit turns ON/OFF the output clock buffer. ...

  • Page 75

    ... De-emphasis is on. GPIO CONTROL REGISTER (Page 02, Address 06h) The GPIO control register controls the GPIO pins of the TSC2302. The direction of each GPIO pin can be set independently. For GPIOs configured as output pins, the data to be driven is written to this register. For GPIO’s configured as inputs, the input data can be read from this register ...

  • Page 76

    ... TSC2302 SLAS394 – JULY 2003 DAC BASS-BOOST FILTER COEFFICIENT REGISTERS (Page 02, Addresses 07h-1Ah) The DAC bass-boost coefficient registers implement the transfer function described. The coefficients are represented by 16-bit twos complement integers with values ranging from -32768 to 32767. The DAC bass-boost coefficient registers are formatted as follows: ...

  • Page 77

    ... Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care must be taken with the physical layout of the TSC2302 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator ...

  • Page 78

    ... TSC2302 SLAS394 – JULY 2003 With this in mind, power to the TSC2302 must be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible on each supply pin to its respective ground pin. A 1-µF to 10-µF capacitor may also be needed if the impedance of the connection between a supply and the power supply is high ...

  • Page 79

    ... TSC2302IRGZ ACTIVE TSC2302IRGZG4 ACTIVE TSC2302IRGZR ACTIVE TSC2302IRGZRG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 80

    ... TAPE AND REEL BOX INFORMATION Device Package Pins TSC2302IRGZR RGZ 48 PACKAGE MATERIALS INFORMATION Site Reel Reel A0 (mm) Diameter Width (mm) (mm) SITE 60 330 16 7.3 Pack Materials-Page 1 4-Oct-2007 B0 (mm) K0 (mm (mm) (mm) Quadrant 7.3 1 Pin1 Q2 ...

  • Page 81

    ... Device Package Pins TSC2302IRGZR RGZ 48 PACKAGE MATERIALS INFORMATION Site Length (mm) Width (mm) SITE 60 342.9 336.6 Pack Materials-Page 2 4-Oct-2007 Height (mm) 28.58 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...