CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 103

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

RTC Register 11: Control/Status Register B (Read/Write)
Bit
7
6
5
4
3
2
1
0
Function
Update Cycle Control:
0:
1:
This bit is not changed when PSRSTB is asserted.
Periodic Interrupt Control:
0:
1:
This bit is cleared when PSRSTB is asserted.
Alarm Interrupt Control:
0:
1:
Alarm interrupts will be generated when the time matches the values programmed into the
alarm register fields.
This bit is cleared when PSRSTB is asserted.
Update-Ended Interrupt Control:
0:
1:
Update-Ended interrupts will be generated when an update cycle is completed. This can be
used to tell the CPU that its data may be read from the clock data registers.
This bit is cleared when PSRSTB is asserted.
Square Wave Control:
0:
1:
Data Mode:
0:
1:
Hour Format Control:
0:
1:
This bit is not changed when PSRSTB is asserted.
Daylight Savings Time Control:
0:
1:
Setting this bit will cause the update cycle to change the time automatically for Daylight
Savings Time. The changes take place on the last Sunday in April and the last Sunday in
October.
This bit is not changed when PSRSTB is asserted.
Enable Update Cycles
Disable Update Cycles, and abort any Update Cycle In Progress
Disable Periodic Interrupt Generation
Enable Periodic Interrupt Generation
Disable Alarm Interrupt Generation
Enable Alarm Interrupt Generation
Disable Update-Ended Interrupt Generation
Enable Update-Ended Interrupt Generation
Disable Square Wave Generation
Enable Square Wave Generation
BCD
Binary
12-hour clock format
24-hour clock format
Disable Daylight Savings Time Change
Enable Daylight Savings Time Change
PRELIMINARY
103
Index=0BH
CY82C693UB
Default
0
0
0
0
0
0
0
0