CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 112

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

CY82C693UB PCI Configuration Registers
The PCI configuration registers for the CY82C693UB are defined in this section. The registers are accessed by performing
configuration read and write cycles (C/BE[3:0]=1010b or 1011b) with the IDSEL signal asserted to the CY82C693UB.
PCI to ISA PCI Configuration Registers (Function 0 during Configuration Cycle)
Register 0: Vendor ID Number (Read Only)
Register 1: Device ID Number (Read Only)
Register 3: Command Register (Read/Write)
Bit
15:0
Bit
15:0
Bit
15:10
9
8
7:4
3
2
1
0
Function
Cypress ID Number: 0001000010000000
Function
CY82C693UB Device ID Number: 1100011010010011
Function
Reserved
Fast Back-to-Back Enable. This bit is forced to 0 (Fast Back-to-Back Accesses are Disabled) 0
SERR Reporting Enable:
0:
1:
Reserved
Enable Special Cycle Decoding:
0:
1:
Bus Master Enable. This bit is forced to 1 (Bus Mastering is Always Enabled)
Memory Access Enable. This bit is forced to 1 (Memory Access is Always Enabled)
I/O Access Enable. This bit is forced to 1 (I/O Access is Always Enabled)
SERR Reporting Disabled
SERR Reporting Enabled
Disable Special Cycle Decoding
Enable Special Cycle Decoding
PRELIMINARY
Index=02H with a 16-bit access
Index=00H with a 16-bit access
Index=04H with a 16-bit access
112
CY82C693UB
Default
1080H
Default
C693H
Default
000000
0
0000
0
1
1
1