CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 126

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 15: Primary Master Drive IDE IOW Command Control Register (Read/Write)
Register 16: Primary Slave Drive IDE IOR Command Control Register (Read/Write)
Register 17: Primary Slave Drive IDE IOW Command Control Register (Read/Write)
Register 18: Primary Master Drive 8-Bit IDE Command Control Register (Read/Write)
Register 19: Primary Slave Drive 8-Bit IDE Command Control Register (Read/Write)
Note: The 8-bit IDE Command Registers are used for mode 0, 1, and 2 drives. For mode 3 and 4 drives, the 8 and 16 bit
timings are the same.
Bit
7:4
3:0
Bit
7:4
3:0
Bit
7:4
3:0
Bit
7:4
3:0
Bit
7:4
3:0
Function
16-Bit Master Drive IDE IOW Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW signal.
16-Bit Master Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
Function
16-Bit Slave Drive IDE IOR Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOR signal.
16-Bit Slave Drive IDE IOR Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOR
must be deasserted between transfers.
Function
16-Bit Slave Drive IDE IOW Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW signal.
16-Bit Slave Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
Function
8-Bit Master Drive IDE Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW or IOR signal.
8-Bit Master Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
Function
8-Bit Slave Drive IDE Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW or IOR signal.
8-Bit Slave Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
PRELIMINARY
126
Index=4EH with an 8-bit access
Index=4FH with an 8-bit access
Index=51H with an 8-bit access
Index=4DH with an 8-bit access
Index=50H with an 8-bit access
CY82C693UB
Default
0110
1110
Default
0011
0011
Default
0110
1110
Default
1010
1010
Default
1010
1010