CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 130

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 8: Secondary IDE Control Address Register (Read/Write)
Note: Register Indices 18H-3BH will return all zeroes when read.
Register 9: Secondary IDE Interrupt INTB Control Register (Read/Write)
Register 10: Secondary IDE Interrupt Pin Control Register (Read Only)
Note: Register Indices 3EH-3FH will return all zeroes when read.
Register 11: Secondary IDE Control Register (Read/Write)
Note: Register Indices 44H-47H will return all zeroes when read.
Bit
31:0
Bit
7:0
Bit
7:0
Bit
31:16
15:14
13
12:11
10
9
8
7:6
5:4
3:2
1:0
Function
Secondary IDE Control Address Register:
This register specifies the amount of I/O space required for the secondary IDE control regis-
ters. The IDE control block requires 2 bytes of I/O space (Bits [1:0] are hardwired to 01). Bits
[15:2] are programmable. Bits [31:16] are hard-wired to 0000H. See stand-alone description
for 32-bit decode option description.
Function
Secondary IDE Interrupt Control Register:
This register is written by the POST software to inform the system which interrupt level the
secondary IDE controller is connected.
Function
Secondary IDE Interrupt Pin Control Register:
02H:
Function
Reserved
Reserved
Retry I/O Accesses Not Completed by 16 PCI Clocks Control:
0:
1:
Reserved
Slave Drive Prefetch Control:
0:
1:
Post Write Control:
0:
1:
Master Drive Prefetch Control:
0:
1:
Reserved
Post Write Length Control:
The value programmed into this register+1 will be the length of the Post Write Bursts that the
IDE write state machine will attempt to the IDE drive when the AT bus grant is received.
Reserved
Prefetch Length Control:
The value programmed into this register+1 will be the length of the Prefetch Bursts that the
IDE read state machine will attempt to the IDE drive when the AT bus grant is received.
The secondary IDE Channel Interrupt is connected to PCI INTB internally.
Disable Prefetch (Must be 0 for CDROM accesses).
Enable Prefetch
One level FIFO for Posted Writes
Four levels of FIFO for Posted Writes
Disable Prefetch (Must be 0 for CDROM accesses)
Enable Prefetch
I/O Accesses Not Completed by 16 PCI Clocks will not be retried
I/O Accesses Not Completed by 16 PCI Clocks will be retried
PRELIMINARY
130
Index=40H with a 32-bit access
Index=14H with a 32-bit access
Index=3DH with an 8-bit access
Index=3CH with an 8-bit access
CY82C693UB
Default
00000000H
Default
15H
Default
02H
Default
00000000000
00000
00
0
00
0
0
0
00
00
00
00