CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 132

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 17: Secondary Master Drive 8-Bit IDE Command Control Register (Read/Write)
Register 18: Secondary Slave Drive 8-Bit IDE Command Control Register (Read/Write)
Note: The 8-bit IDE Command Registers are used for mode 0, 1, and 2 drives. For mode 3 and 4 drives, the 8 and 16 bit
timings are the same.
Register 19: Secondary Master Drive IORDY Control Register (Read/Write)
Bit
7:4
3:0
Bit
7:4
3:0
Bit
7:4
3:2
1:0
Function
8-Bit Master Drive IDE Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW or IOR signal.
8-Bit Master Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
Function
8-Bit Slave Drive IDE Command Pulse Width Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) of the
asserted IOW or IOR signal.
8-Bit Slave Drive IDE IOW Command Recovery Time:
The value programmed into this register +1 will be the duration (in PCI Clock cycles) that IOW
must be deasserted between transfers.
Function
Reserved
Read Synchronization Control:
The value in this register selects the number of PCI clocks used to synchronize the rising
edge of IORDY during read transactions.
Write Synchronization Control:
The value in this register selects the number of PCI clocks used to synchronize the rising
edge of IORDY during write transactions.
PRELIMINARY
132
Index=52H with an 8-bit access
Index=51H with an 8-bit access
Index=50H with an 8-bit access
CY82C693UB
Default
1010
1010
Default
1010
1010
Default
0000
01
01