CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 136
CY82C693UB
Manufacturer Part Number
CY82C693UB
Description
Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY82C693UB.pdf
(164 pages)
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Register 12: Interrupt Pin Register (Read/Write) - Index=3DH with an 8-bit access
Register 13: Min_Gnt Register (Read Only) - Index=3EH with an 8-bit access
Register 14: Max_Lat Register (Read Only) - Index=3FD with an 8-bit access
Register 15: ASIC Test Mode Enable Register (Read/Write) - Index=40H with a 32-bit access
Register 16: ASIC Operational Mode Enable Register (Read/Write) - Index=44H with an 8-bit access
Bit
7:0
Bit
7:0
Bit
7:0
Bit
31:0
Bit
7:0
Function
Interrupt Pin Register. This register identifies which interrupt pin a device uses. Since the
USB Host Controller uses INTA, this register is set to 01H.
Function
PCI Min_Gnt. This register specifies how long of a burst the USB Host Controller needs
assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 micro-
second.
Function
PCI Max. Latency. This register specifies how often the USB Host Controller needs access
to the PCI bus assuming a clock rate of 33 MHz. The value specifies a period of time in units
of 1/4 microsecond.
Function
ASIC Test Mode Enable. For normal USB Host Controller operation this register must be set
to 0.
Function
ASIC Operational Mode Enable. For normal USB Host Controller operation this register must
remain as 0.
PRELIMINARY
136
CY82C693UB
Default
01H
Default
00H
Default
00H
Default
0XXXXXXXH
Default
00H
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