CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 138

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 2: HcCommandStatus (Read/Write) - Offset=08H with a 32-bit access
Register 3: HcInterruptStatus (Read/Write) - Offset=0CH with a 32-bit access
Bit
31:18
17:16
15:4
3
2
1
0
Bit
31
30
29:7
6
5
4
3
2
1
0
Function
Reserved.
Schedule Overrun Count:
This field increments every time the SchedulingOverrun bit in HcInterruptStatus is set. The
count wraps from ‘11’ to ‘00’.
Reserved.
Ownership Change Request:
When set by software, this bit sets the OwnershipChange field in HcInterruptStatus. The bit
is cleared by software.
Bulk List Filled:
When set, this bit indicates there is an active ED on the Bulk List. the bit may be set by either
software or the Host Controller. The bit is cleared by the Host Controller each time it begins
processing the head of the Bulk List
Control List Filled:
When set, this bit indicates there is an active ED on the Control List. The bit may be set by
either software or the Host Controller. The bit is cleared by the Host Controller each time it
begins processing the head of the Control List
Host Controller Reset:
This bit is set to initiate a software reset. This bit is cleared by the Host Controller upon
completion of the reset operation
Function
Reserved.
Ownership Change:
This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set.
Reserved.
Root Hub Status Change:
This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register
has changed
FrameNumber Overflow:
This bit is set when bit 15 of FrameNumber changes value from ‘0’ to ‘1’ or from ‘1’ to ‘0’.
Unrecoverable Error:
Read Only. This event is not implemented and is hard-coded to ‘0’. All writes are ignored.
Resume Dectected:
This bit is set when the Host Controller detects resume signaling on a downstream port.
Start Of Frame:
This bit is set when the Frame Management block signals a ‘Start of Frame’ event.
Writeback Done Head:
This bit is set after the Host Controller has written HcDoneHead to HccaDoneHead.
Scheduling Overrun:
This bit is set when the List Processor determines a Schedule Overrun has occurred.
PRELIMINARY
138
CY82C693UB
Default
00
0H
0
0
0
0
Default
0
0
0H
0
0
0
0
0
0
0