CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 147

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Register 22: HceInput - Index=104H with a 32-bit access
Note: This register is the emulation side of the legacy Input Buffer Register.
Register 23: HceOutput - Index=108H with a 32-bit access
Note: This register is the emulation side of the legacy Output Buffer register where keyboard and mouse data is to be
read by software.
Register 24: HceStatus (Read/Write) - Index=10CH with a 32-bit access
Note: This register is the emulation side of the legacy Status register.
Bit
31:8
7:0
Bit
31:8
7:0
Bit
31:8
7
6
5
4
3
2
1
0
Function
Reserved.
Input Data:
This register holds data that is written to I/O ports 60H and 64H.
Function
Reserved.
Output Data:
This register hosts data that is returned when an I/O read of port 60H is performed by appli-
cation software.
Function
Reserved.
Parity:
Indicates parity error on keyboard/mouse data.
Timeout:
Used to indicate a time-out.
Aux Output Full:
IRQ12 is asserted whenever this bit is set to ‘1’ and OutputFull is set to ‘1’ and the IRQEn bit
is set.
Inhibit Switch:
This bit reflects the state of the keyboard inhibit switch and is set if the keyboard is NOT
inhibited.
Cmd Data:
The Host Controller will set this bit to ‘0’ on an I/O write to port 60H and on an I/O write to
port 64H the Host Controller will set this bit to ‘1’.
Flag:
Nominally used as a system flag by software to indicate a warm or cold boot.
Input Full:
Except for the case of a Gate A20 sequence, this bit is set to ‘1’ on an I/O write to address
60H or 64H. While this bit is set to ‘1’ and emulation is enabled, an emulation interrupt
condition exists.
Output Full:
The Host Controller will set this bit to ‘0’ on a read of I/O port 60H. If IRQEn is set and
AuxOutputFull is set to ‘0’ then an IRQ1 is generated as long as this bit is set to ‘1’. If IRQEn
is set and AuxOutputFull is set to ‘1’ then an IRQ12 will be generated as long as this bit is
set to ‘1’. While this bit is ‘0’ and CharacterPending in HceControl is set to ‘1’, an emulation
interrupt condition exists.
PRELIMINARY
147
CY82C693UB
Default
0H
-
Default
0H
-
Default
0H
0
0
0
0
0
0
0
0