CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 17

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Introduction
System Overview
The hyperCache family is a family of chips created to provide
flexible solutions for today’s PC designs. The chipset provides
all the functions necessary to implement a 3.3V Pentium-class
processor based system with the USB (Universal Serial Bus),
PCI (Peripheral Component Interconnect), and the ISA (Indus-
try Standard Architecture) buses. System designers can ex-
ploit the advantages of the USB and PCI buses while maintain-
ing access to the large base of ISA cards in the marketplace.
The Cypress hyperCache family offers system designers sev-
eral key advantages. With only three chips, a complete system
can be implemented. Cache can be added up to 512 MB with
additional CY82C694 devices in 128-KB increments All
chipset solutions are pin-compatible and provide flexible up-
grade paths through on-board or external cache modules. Six
banks of page-mode or EDO DRAM further increase the sys-
tem designer’s options. The chipset also contains concurrent
bus support, PCI enhanced IDE with CD-ROM support, inte-
grated RTC, integrated peripheral control (Interrupts/DMA),
and integrated keyboard controller. This chipset is flexible
enough to provide the system designer with many cost/perfor-
mance/function options to provide an optimum solution for a
given design.
CY82C693UB Introduction
The CY82C693UB Peripheral Controller provides a highly in-
tegrated peripheral solution for PCI-based motherboards. The
CY82C693UB contains a PCI to ISA bridge, a PCI IDE con-
troller, DMA controllers, Interrupt controllers, a Real-
Time-Clock, Keyboard controller and a USB Host Controller.
Figure 1 shows a block diagram of the CY82C693UB.
Functional Overview
The CY82C693UB Peripheral Controller contains the following
functional blocks:
PCI Bus Interface
The CY82C693UB provides a bridge for transactions between
the PCI bus, the ISA bus, and IDE peripherals. PCI bus speeds
of 25, 30, or 33 MHz are supported. The PCI interface is mas-
ter/slave (it can initiate or be a target for transactions). The PCI
bus interface in the CY82C693UB is Revision 2.1 compliant.
This standard allows for a multitude of high-speed peripheral
• PCI Interface
• ISA Interface
• Reset Logic
• Keyboard Controller
• Power Management Logic
• AT Refresh Logic
• Pre-Read/Post-Write Buffers
• BIOS ROM Control
• Timer/Counter Logic
• DMA Controllers
• Dual-Channel Enhanced IDE Controller
• Real-Time-Clock with 32-kHz Oscillator
• Interrupt Controllers
• USB Host Controller
PRELIMINARY
17
cards to be added to the system. PCI is the predominant local
bus for Pentium systems.
Master cycles are initiated by driving FRAME LOW with a valid
address on AD[31:0], valid even address parity on PAR, and a
valid command on C/BE[3:0]. Data phases occur when IRDY
(initiator ready) and TRDY (target ready) are both active, valid
data is placed on AD[31:0], the PAR signal is driven to reflect
even parity, and the correct byte enable combination is present
on C/BE[3:0]. Wait states can be inserted into a transaction if
the initiator deasserts IRDY or the target deasserts TRDY. A
transaction is terminated by the deassertion of FRAME prior
to the final data phase. As a PCI master, the CY82C693UB will
only perform memory read and write transactions. A read or
write cycle consists of a maximum of 4 bytes of data in a single
data cycle.
The CY82C693UB uses a subtractive decode strategy to de-
termine if a PCI target transaction is destined for the ISA bus.
Potential PCI targets decode any valid address during the first
cycle of the transaction (FRAME asserted). If a PCI peripheral
device (including the integrated IDE controller in the
CY82C693UB) detects a transaction to its address space, it
will assert DEVSEL. If the CY82C693UB does not detect the
assertion of DEVSEL by another target (or its own IDE control-
ler) within 4 PCI clock cycles, it will claim the transaction by
asserting DEVSEL. All transactions that are not claimed by a
PCI peripheral are, by default, sent to the ISA bus. After as-
serting DEVSEL, the CY82C693UB will initiate an ISA cycle
and assert TRDY to the PCI bus when valid data is available.
As a PCI slave, the CY82C693UB will target-terminate the cy-
cle after the first data transfer by asserting STOP with TRDY if
FRAME is not deasserted before the data phase. The
CY82C693UB does not accept bursts as a target. By not al-
lowing target bursts, PCI bus bandwidth, which would other-
wise be quickly consumed by ISA or IDE targets, is conserved.
The CY82C693UB supports PCI error reporting through the
SERR (system error) signal. Both internally detected and ex-
ternally generated errors are reported. SERR is asserted for
any system error, including address/data parity errors on Spe-
cial Cycle commands, except for data parity. If the
CY82C693UB detects the assertion of SERR, it will assert
NMI (non-maskable interrupt) to the CPU. The CY82C693UB
will store the source of the NMI (SERR) in an internal configu-
ration register to allow the NMI handler software to determine
the cause of the error.
The CY82C693UB supports the four PCI interrupt signals
(INTA, INTB, INTC, and INTD). The interrupt lines are
open-drain and should be routed to all of the PCI slots. For
single-function devices, only INTA should be used. The three
other interrupt lines can be connected to any set of functions
on a multi-function device. Each interrupt signal can be pro-
grammed to be level-sensitive (PCI Compliant) or edge-trig-
gered (not PCI Compliant). The assertion of a PCI interrupt
request will cause the INTR signal to be asserted to the pro-
cessor. When the processor performs an interrupt acknowl-
edge cycle, the CY82C693UB will return an interrupt vector
based on the level of the PCI interrupt. The PCI interrupt levels
are programmable. Interrupt programmability is useful in re-
solving system conflicts.
The
CY82C693UB supports up to five PCI masters, including the
CY82C691. There are four dedicated request and grant line
pairs, one for each slot, and a special busy and grant for the
CY82C693UB
contains
the
CY82C693UB
PCI
arbiter.
The