CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 19

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

CPURST is an active HIGH signal that provides power-on re-
set functionality for the CPU. CPURST is asserted when the
CY82C693UB detects PWGD (power good) asserted from the
power supply. CPURST forces the processor to begin execu-
tion in a known state. When the Pentium processor detects
CPURST, it will immediately abort all bus activity and perform
its reset sequence. The CY82C693UB will assert CPURST for
a minimum of 1 ms after PWGD is asserted. This is sufficient
to ensure a “cold” or “power-on” reset. The assertion of
CPURST will cause all internal processor registers, write-buff-
ers, and caches to be reset. The processor will begin execution
by reading from address FFFFFFF0H upon the deassertion of
CPURST. CPURST is also used to reset ISA peripherals (func-
tions as SYSRESET).
For a “warm” reset, INIT will be asserted for a minimum of 15
PCI clock cycles. A “warm” reset is performed whenever the
CPU writes Port 92H, bit 0, to “1”. The keyboard controller
within the CY82C693UB can also issue a fast “warm” reset if
the user writes FE (hex) to port 64 (hex). INIT provides
CPURST functionality except INIT leaves the CPU’s level 1
cache, internal write-buffers, and floating-point registers intact.
Only the processor core is reset. INIT can be used to switch
the processor from protected to real mode. Once INIT is sam-
pled active, the processor will begin the initialization sequence
on the next instruction boundary. The initialization sequence
will continue to completion followed by normal reset execution
(read from address FFFFFFF0H). INIT will be asserted for a
minimum of two CPU clock cycles and will remain active for
three CPU clock cycles prior to the BRDY of an I/O write cycle.
RESET is used to reset all PCI peripherals (functions as
PCIRST). RESET (like CPURST) will be asserted for a mini-
mum of 1 ms after PWGD is asserted.
Keyboard Controller
The CY82C693UB integrates the essential functions of an
8042 Keyboard Controller including:
Operating Frequency
The keyboard controller inside the CY82C693UB operates at
frequencies between 6 and 16 MHz. The clock is internally
selectable.
Resetting the Keyboard Controller
The keyboard controller will be reset when the PWGD (power
good) signal is negated. Once PWGD is asserted, the key-
board controller will remain in its reset state for 120 keyboard
clock cycles before becoming operational.
Host Interface
PCI or ISA masters communicate with the keyboard controller
by performing I/O reads and writes to two eight-bit port loca-
tions (0064H and 0060H). I/O Port 0064H is the command/sta-
tus register and I/O Port 0060H is the data register. There are
two host signals that the keyboard controller generates (or are
functionally emulated within the CY82C693UB), GTA20 and
INIT. These signals initiate the A20 mask and “warm reset”
respectively. There are also four keyboard general purpose I/O
• operating frequencies from 6 to 16 MHz
• support for a PS/2-compatible mouse
• complete operating system independence
• works with MS-DOS , Microsoft Windows , OS/2 , and
UNIX
PRELIMINARY
19
registers and ports that are user definable. As inputs, they set
bits in internal reserved registers. As outputs, they reflect the
value of the internal register bits. The general purpose I/Os are
multiplexed with some alternate control signals, the XD bus,
IDE DMA control, and IDE Interrupt Request signals. There-
fore, these system functions will not be available from the
CY82C693UB when the pins are programmed as general pur-
pose I/Os. However, not every system will require the addition-
al system functions, and those that do can implement these
system functions externally if general purpose I/O is a require-
ment.
PS/2 Compatible Mouse Support
The CY82C693UB supports a PS/2 compatible mouse.
MSCLK and MSDATA should be connected directly to the
mouse connector. Mouse interrupt requests are generated in-
ternally.
Keyboard Interface
The CY82C693UB provides the KBCLK and KBDATA signals
to connect directly to the keyboard controller. There is also a
KEYLOCK pin which should be connected to the KEYLOCK
connector. If KEYLOCK is active, the keyboard controller will
not respond to inputs from the keyboard. The keyboard inter-
rupt request is internally connected to the CY82C693UB’s in-
terrupt controller.
Maximum Flexibility
The internal keyboard controller can be disabled if a custom,
external keyboard controller solution is desired. All of the sig-
nals needed to control and interface to an external keyboard
controller are multiplexed with existing keyboard interface sig-
nals.
Keyboard Self-Test
The first access to the keyboard controller must be a write of
AAH to port 64H. This initiates the keyboard self-test. A sub-
sequent read of port 64H will issue 55H if self-test is passed.
Prior to the write of AAH to port 64H, all keyboard controller
accessed will be ignored.
Power Management Logic
The CY82C693UB provides flexible power management to
help systems conform to governmental system power con-
sumption guidelines. There are 5 timers within the power man-
agement logic (a standby timer, a suspend timer, user timer 1,
user timer 2, and user timer 3). There are also 10 programma-
ble event detectors.
Events which can be monitored include:
The CY82C693UB can monitor any combination or all of the
above events.
• Keyboard Commands
• Serial Port Commands
• Parallel Port Commands
• Hard Disk Commands
• DMA/ISA MASTER Requests
• A Specific (set of) Interrupt Request(s)
• Video Memory Accesses
• Floppy Drive Accesses
• A PCI Master Request
• A Specific I/O Range
CY82C693UB