CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 23

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

PCI and IDE interrupts are fully routable internally to indepen-
dent interrupt levels. The interrupt level of each PCI or IDE
interrupt is controlled with configuration registers.
NMI Sources
The CY82C693UB can generate a non-maskable interrupt
(NMI) from the following sources:
1. ISA bus IOCHK assertion.
2. PCI SERR assertion.
Please refer to port 61H and port 70H description for enable
and disable options.
Stand-Alone Operation
The CY82C693UB was designed to be used as part of the
hyperCache chipset or as a stand-alone PCI peripheral con-
troller. The stand-alone option can be used in any PCI system.
The system CPU need not be X86-based, provided the PCI
specification is followed. Special options were added to the
CY82C693UB to make stand-alone operation very flexible.
The options include: the ability to disable the integrated PCI
arbiter; the ability to split the GNTBSY signaling protocol onto
separate GRANT and BUSY signals; the ability to reset both
the CY82C693UB and the ISA bus when PCIRST is driven
active from an external source; the ability to bypass the
FREQACK protocol for DMA transfers into memory; and the
ability to decode 32-bit I/O space.
Use With An External PCI Arbiter
When using an external PCI arbiter, GNT3/DISARB (pin 194)
should be tied LOW through a 1K Ohm pull-down resistor. This
will disable the PCI arbiter that is contained in the
CY82C693UB.
Pin 191 becomes the PREQ output when the internal arbiter
is disabled. PREQ is the primary PCI request signal. In the
CY82C693UB, PREQ is used to request the PCI bus for ISA
DMA/Master transactions, Bus Master IDE transactions, and
USB bus master transactions. PREQ should be connected to
one of the request inputs of the external arbiter.
Pin 196 becomes the PGNT input when the internal arbiter is
disabled. PGNT is the primary PCI grant signal. The external
arbiter should assert PGNT to allow the CY82C693UB to take
ownership of the PCI bus. PGNT should be connected to the
grant output that corresponds to the PREQ request input. If
PGNT is asserted to the CY82C693UB without a pending
PREQ, the CY82C693UB will follow bus parking rules as spec-
ified in the PCI rev. 2.1 specification.
Pin 192 becomes the SREQ input when the internal arbiter is
disabled. SGNT is the secondary PCI grant signal. Pin 198
becomes the SGNT output when the internal arbiter is dis-
abled. They are used as optional USB arbitration signals.
SREQ and SGNT can be programmed to provide separate
arbitration for the USB Host Controller. By default, the USB
Host Controller requests use of the PCI bus and is granted the
bus through PREQ and PGNT. When programmed for sepa-
rate arbitration (PCI Configuration Registers, Function 0, in-
dex=4DH, bit 7), SREQ and SGNT are used to arbitrate for
USB, and PREQ and PGNT are used for other bus masters
(IDE and ISA DMA).
The integrated Real-Time-Clock contains logic to generate a
square wave. When the internal PCI arbiter is enabled, the
RTC square wave is
not available outside of the
PRELIMINARY
23
CY82C693UB. When the internal PCI arbiter is disabled, the
RTC square wave is driven on pin 193.
Splitting GNTBSY
When the PCI arbiter inside the CY82C693UB is enabled,
GNTBSY functions as the arbitration signal between the
CY82C693UB and the CPU-to-PCI bridge. The CPU-to-PCI
bridge is normally granted use of the PCI bus (to reduce the
arbitration latency that can hurt CPU performance). The
CY82C693UB holds GNTBSY asserted to signal that the bus
is granted to the CPU-to-PCI bridge. When another PCI mas-
ter requests use of the bus, the CY82C693UB takes away the
CPU-to-PCI bridge’s grant by deasserting GNTBSY for one
clock cycle and then placing GNTBSY in a high-impedance
state. The CPU-to-PCI bridge must signal busy (by reasserting
GNTBSY) in the cycle immediately following the sampling of
GNTBSY deasserted if the CPU-to-PCI bridge wishes to retain
control of the PCI bus. Otherwise, the CPU-to-PCI bridge must
immediately get off of the PCI bus. If GNTBSY is not sampled
asserted in the next clock cycle after the original deassertion,
the CY82C693UB will grant the PCI bus to the highest priority
requesting master. However, if GNTBSY is reasserted by the
CPU-to-PCI bridge, the CY82C693UB will not grant the bus to
any other PCI masters until GNTBSY is deasserted again by
the CPU-to-PCI bridge. Busy must be asserted until the PCI
bus is IDLE; otherwise, the CY82C693UB may cause a bus
clash. This is because the CY82C693UB will not check for PCI
bus IDLE if it sees that busy is deasserted. If the PCI bus has
not been signalled busy by the CPU-to-PCI bridge, a maximum
of three pending requests will be serviced before GNTBSY is
asserted again by the CY82C693UB to grant the bus back to
the CPU-to-PCI bridge.
The GNTBSY protocol is implemented using a single signal.
This may cause problems when attempting to interface the
CY82C693UB to a CPU-to-PCI bridge that does not support
single signal handshaking. Therefore, the CY82C693UB pro-
vides the option to separate GNTBSY into a GRANT signal
and a BUSY signal.
If pin number 179 (SMI/GBSEP) is pulled down through a 1K
Ohm resistor, the GNTBSY signalling protocol is split into sep-
arate GRANT and BUSY signals. Pin 189 becomes a con-
stantly driving GRANT output. GRANT will be asserted to
grant ownership of the PCI bus to the CPU-to-PCI bridge. Pin
163 becomes the BUSY input. BUSY is asserted by the
CPU-to-PCI bridge to signal that the PCI bus is busy and
should not be granted to any other PCI master.
PCICLK
GNTBSY
CY82C693UB takes
the grant away
Figure 3. GNTBSY Arbitration Protocol
CPU-to-PCI bridge
signals busy
CY82C693UB