CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 25

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

CY82C693UB without any extra logic. An external hub can be
connected to any of the two integrated ports in case more de-
vices are required. The Host Controller is connected to system
memory via the PCI bus and has bus mastering capability. The
USB Host Controller’s PCI configuration registers are located
in PCI function 3 configuration space in CY82C693UB.
The CY82C693UB USB Host Controller fully complies with the
USB Open Host Controller Interface (OpenHCI) standard, thus
allowing it to be compatible with the available OpenHCI stan-
dard software drivers. Figure 4 illustrates different hierarchical
domains of a USB system.
The domains are the USB Driver (USBD), Host Controller Driv-
er (HCD), Host Controller (HC), and USB Device. The USB
Driver and the Host Controller Driver are part of system soft-
ware, and HCD is typically provided by the operating system.
The Host Controller and the USB devices are implemented in
hardware. The interface between the software layer (HCD) and
the hardware (HC) is called Host Controller Interface (HCI),
which is specified in the OpenHCI standard. The basic building
block for communication across the interface is called Transfer
Descriptor (TD). The Transfer Descriptor contains all neces-
sary information for the Host Controller to process packet
transaction with USB devices. The HCD software is responsi-
ble for communicating information between the USBD soft-
ware layer (also typically located in the operating system) and
the Host Controller. The HCD receives Transfer Descriptors
CY82C693UB Signal Description
The CY82C693UB signals are divided into eight functional ar-
eas: Reset signals, PCI Interface signals, ISA Interface sig-
nals, Power Management signals, Keyboard Interface signals,
Reset Signals
PCI Interface Signals
Name
PWGD
CPURST
PCIRST
INIT
Name
AD[31:0]
PCICLK
I/O
I
O
O
O
I/O
I/O
I
PRELIMINARY
Description
Power Good: This signal is driven active from a combination of the external power
supply’s power good signal and the external reset switch. This signal is used to qualify
initialization signals and reset the internal state of the CY82C693UB.
CPU Reset: This signal resets the CPU and the ISA bus.
PCI Reset: This signal functions as the PCI bus reset. During normal operation, this
signal is an output only (used by the CY82C693UB to reset PCI bus residents). If pin
172 is pulled LOW through a 1K Ohm resistor, PCIRST becomes an input that is used
to initiate a CY82C693UB reset and an ISA reset. See the text description for
Stand-Alone Operation. This signal will power up in a high-impedance state with an
internal pull-up resistor. When pin 172 is sampled, this signal will either begin driving
(pin 172 HIGH) or remain a high-Z input (pin 172 LOW).
CPU Initialization: This signal is used to reset the core of the CPU without disturbing
the state of internal caches or write-buffers. This signal can be used to switch the
processor from protected mode to real mode.
Description
PCI Address/Data Bus: Multiplexed bidirectional address/data lines on the PCI bus.
The CY82C693UB either drives or samples these lines during PCI cycles.
PCI Clock: PCI Clock Input. This signal is used to synchronize the CY82C693UB to
the PCI bus. The clock must be within the range 25 MHz to 33 MHz.
25
from the USBD, reformats them as necessary, schedules their
execution and enqueues them for the processing by the Host
Controller. When the Host Controller finishes the processing
of the Transfer Descriptors, the HCD reformats them as nec-
essary, and sends the results back to the USBD. The HCD is
also responsible for status and error conditions monitoring.
The Host Controller moves data between system memory and
devices on the USB by processing Transfer Descriptors en-
queued by the HCD and generating transactions on USB.
When the Host Controller sends information to a USB device,
the data from system memory pointed to by a Transfer De-
scriptor is converted to the USB serial protocol and transferred
on the USB with the appropriate headers. When the Host con-
troller receives information from a USB device, the data is con-
verted from the USB serial protocol and stored in the system
memory location pointed to by a Transfer Descriptor. The Host
Controller is also responsible for reporting the status of trans-
actions on USB to the HCD. Some other tasks performed by
the Host Controller include the maintenance of USB frame
generation and the reporting of USB device connection activity
to the HCD.
For more detailed information on the USB Host Controller, see
USB Open Host Controller Interface (OpenHCI) Specification,
revision 1.0 available from Microsoft, Compaq and National
Semiconductor. For additional information on USB, see USB
Specification revision 1.0 from USB Implementers Forum.
IDE Interface signals, USB interface signals, and Miscella-
neous signals.
CY82C693UB