CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 26

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

PCI Interface Signals (continued)
Name
C/BE[3:0]
FRAME
IRDY
TRDY
DEVSEL
PAR
STOP
SERR
IDSEL
INTA/B/C/D
GNTBSY/GRANT
FREQACK/IRQ8
REQ[3:2]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I
PRELIMINARY
Description
PCI Command & Byte Enables: C/BE[3:0] are driven by the current bus master during
the address phase to define the transaction and during the data phase as the byte
enables. These signals are outputs when the CY82C693UB is a master and inputs
when the CY82C693UB is a slave.
Cycle Frame: Driven by the current bus master to indicate the start and duration of a
transaction.
Initiator Ready: The assertion of IRDY indicates the current bus master’s ability to
complete the current data phase of the transaction. Used in conjunction with TRDY
from the target.
Target Ready: The assertion of TRDY indicates the current target’s ability to complete
the current data phase of the transaction. Works in conjunction with IRDY from the
master.
Device Select: Indicates that a PCI device has decoded that it is the target of the
transaction. The target has three options for decoding: fast decoding, medium decod-
ing, or slow decoding. The CY82C693UB will sample DEVSEL, and if it is not asserted
by a target within the timeout period, will assert DEVSEL to claim the cycle.
Parity: An even parity bit across AD[31:0] and C/BE[3:0]. As a master the CY82C691
generates even parity on PCI write cycles. On read cycles, the CY82C693UB checks
parity by sampling PAR.
Stop: Indicates that the current target is requesting the master to stop the current
transaction. STOP is used in conjunction with DEVSEL and TRDY to indicate discon-
nect, target abort, and retry cycles.
System Error: System error may be asserted by any agent for reporting address parity
errors or any other types of errors besides data parity. SERR will cause the
CY82C693UB to assert NMI to the processor.
PCI ID Select: This signal should be connected to a unique PCI address. It is used to
select the CY82C693UB during PCI configuration cycles.
PCI Interrupt Requests: These signals allow PCI peripherals to interrupt the processor.
CY82C691 Busy/Grant: This signal is the PCI arbitration signal used by the CY82C691.
The CY82C691 is the default owner of the PCI bus. In the default state, the
CY82C693UB will actively drive this signal asserted (LOW). If another external master
requests the bus, the CY82C693UB will deassert this signal for a single clock cycle
and then let the signal float. If the CY82C691 asserts this signal within two clock cycles
after this signal is seen deasserted, this signal becomes BUSY to the central arbiter.
BUSY tells the CY82C693UB that the CY82C691 owns the PCI bus. The
CY82C693UB will not grant the PCI bus to any other PCI master until BUSY is deas-
serted by the CY82C691. When no requests are pending on the PCI bus, this signal
reverts to 691 GRANT and is driven active (LOW) to allow the CY82C691 to take
possession of the PCI bus. If pin 179 is strapped LOW through a 1K Ohm resistor, this
signal becomes a dedicated GRANT output. GRANT is constantly driven by the
CY82C693UB.
CY82C691 Flush Request/Acknowledge or RTC Interrupt Request: This signal is used
to facilitate DMA transfers. The CY82C693UB will drive this signal LOW for one clock
cycle to request the CY82C691 flush its internal buffers before a DMA transfer. Once
the CY82C691 has flushed its buffers, it will drive this signal for one clock cycle to
acknowledge the flush. The CY82C693UB is then free to perform its DMA transfer.
If PCI configuration register 4DH, bit 6 is set to “1”, all flush requests are immediately
acknowledged inside the CY82C693UB. This signal becomes high-impedance.
If PCI configuration register 4DH, bit 5 is also set to “1”, the Real-Time-Clock interrupt
request (IRQ8) is masked to the internal interrupt controller and driven out on this pin.
PCI Bus Requests: These signals are connected to the individual bus requests from
each PCI peripheral. When a combination of the bus requests is asserted, the
CY82C693UB will resolve the priority and give the grant to the highest priority master.
If the internal PCI arbiter is disabled (by strapping pin 194 LOW through a 1K Ohm
resistor), these signals become UNUSED.
26
CY82C693UB