CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 32

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

ISA Interface Signals (continued)
Name
GTA20/ROMS0
X2/RTCRD
X1/RTCWT
IOCS16
MCS16
SBHE
MRD
MWT
IOR
IOW
SMEMR
SMEMW
I/O
I/O
O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRELIMINARY
Description
Gate A20: This signal forces memory to wrap-around 1 MB. It is implemented as a fast
gate A20.
At power-up, this signal acts as ROMS0. ROMS0 is used in conjunction with ROMS1
(IGNNE) and ROMMODE (ROMCS) to implement boot-block Flash recovery straps.
The strapping is defined as follows:
ROMMODE
RTC Crystal Out/RTC Output Enable: If the integrated RTC is used, this signal is the
32.768-kHz crystal output. If an external RTC is desired, this signal is the RTC output
enable. NOTE: external RTC is a bond option only.
This input must be open if a crystal oscillator with TTL outputs are used to signal 32.768
KHz. The 32.768 KHz oscillator output should be connected to X1.
RTC Crystal In/RTC Write Enable: If the integrated RTC is used, this signal is the
32.768-KHz crystal input. If an external RTC is desired, this signal is the RTC write
enable.NOTE: external RTC is a bond option only.
A TTL level 32.768 KHz oscillator may be connected to this pin. If a oscillator is con-
nected to this pin, X2 should be left open.
16-Bit I/O Chip Select: This signal is driven active by any ISA I/O target that can support
16-bit accesses.
16-Bit Memory Chip Select: This signal is driven active by any ISA MEMORY target
that can support 16-bit accesses. During ISA Master cycles, the CY82C693UB will
drive this signal.
System Byte High Enable: This signal is driven active by the current ISA bus master
to indicate that valid data resides on SD[15:8].
ISA Memory Read Command Signal: This signal is driven by the current ISA bus owner
to request a memory resource to drive data onto the bus during a cycle.
ISA Memory Write Command Signal: This signal is driven by the current ISA bus owner
to request a memory resource to accept data presented on the bus during a cycle.
ISA I/O Read Command Signal: This signal is driven by the current ISA bus owner to
request an I/O resource to drive data onto the bus during a cycle.
ISA I/O Write Command Signal: This signal is driven by the current ISA bus owner to
request an I/O resource to accept data presented on the bus during a cycle.
ISA System Memory Read Command Signal: This signal is driven by the current ISA
bus owner to request a memory resource to drive data onto the bus during a cycle.
This signal is only active within the first 1 MB of memory space.
ISA System Memory Write Command Signal: This signal is driven by the current ISA
bus owner to request a memory resource to accept data presented on the bus during
a cycle. This signal is only active within the first 1 MB of memory space.
1
0
0
0
0
ROMS0
X
1
1
0
0
32
ROMS1
X
1
0
1
0
Result
No ROM address bits are
inverted. (EPROM or boot-
block recovery mode)
ROM address bit 16 is inverted
(Normal operation w/ 16Kx8
boot-block Flash)
ROM address bit 17 is inverted
(Normal operation with 32Kx8
boot-block Flash)
ROM address bit 18 is inverted
(Normal operation with 64Kx8
boot-block Flash)
ROM address bit 15 is inverted
(Normal operation with 8Kx8
boot-block Flash)
CY82C693UB