CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 33

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

ISA Interface Signals (continued)
Power Management Signals
Keyboard Interface Signals
IDE Interface Signals
Name
OSC
0WS
AEN
IOCHRDY
IOCHK
Name
SMI/GBSEP
STOPCLK/
RSTCHG
EPMI
Name
KBDATA
KBCS/KYLCK
MSDATA/KBDCLK
Name
IDEIOR
IDEIOW
IDEIOCS16
I/O
I
I
O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
O
O
I
PRELIMINARY
Description
Oscillator Input: This signal is the 14.318-MHz reference clock input, used by the timer
and DMA controller. This reference clock must be connected, because it is used to
sample strap options.
Zero Wait State Input: When this signal is driven by an ISA peripheral, the
CY82C693UB will shorten the ISA cycle to zero wait states and ignore IOCHRDY.
Address Enable: This signal is driven active by the CY82C693UB as an indication to
the I/O resources not to respond to the address and I/O Command signal lines during
a DMA cycle.
I/O Channel Ready: When deasserted, this signal indicates to the ISA bus owner that
additional cycle time is required to complete the transaction. Used to add ISA wait
states.
I/O Channel Check: This signal is driven active if the system detects an ISA bus parity
error.
Description
System Management Interrupt/GNTBSY Separate: Used by the CY82C693UB to send
the highest-level, process-transparent interrupt to the CPU. At power up, this signal is
sampled to determine the grant/busy protocol for CPU-to-PCI bridge arbitration. If this
signal is left floating (sampled HIGH), GNTBSY arbitration is performed on a single
signal. If this signal is strapped LOW through a 1K Ohm resistor, GRANT is driven out
on pin 189 and BUSY is sampled on pin number 163.
CPU Stop Clock/External PCI Reset Generator Present: This signal is used to stop the
clock to the CPU’s core to reduce power-consumption during idle periods. At power
up, this signal is sampled to determine the source of PCI reset in the system. If this
signal is left floating (sampled HIGH), PCI reset and CPU/ISA reset signals are output
from the CY82C693UB. They are asserted when PWGD is sampled deasserted and
will be driven asserted for a minimum period of 1ms after PWGD goes active. If
STOPCLK/RSTCHG is strapped LOW through an external 1K Ohm resistor, PCIRST
becomes an input. When PCIRST is sampled asserted, all registers/FIFOs/state within
the CY82C693UB are cleared to a known reset state. CPURST is driven active for the
duration of PCIRST active. There is no minimum guaranteed assertion time for
CPURST in this mode.
External Power Management Input: This signal is used to force the assertion of an SMI
by an external source (e.g., a power-down switch).
Description
Keyboard Data: This is the serial data line to/from the keyboard connector.
Keyboard Chip Select/Key Lock Input: This signal is the key lock input to lock the
keyboard (for system security) if the internal keyboard controller is used. If an external
keyboard controller is desired, this is the keyboard controller chip select.
Mouse Data/External Keyboard Controller Clock Output: If the internal keyboard con-
troller is used, this is the serial mouse data line to/from the keyboard connector. If an
external keyboard controller is desired, this signal drives the state machine clock input
(normally ATCLK) of the external keyboard controller.
Description
IDE I/O Read: This signal directly drives the IDEIOR signal on the IDE connector.
IDE I/O Write: This signal directly drives the IDEIOW signal on the IDE connector.
IDE I/O Chip Select 16: This signal directly drives the IDEIOCS16 signal on the IDE
connector. Determines whether the IDE transaction is 8 bits or 16 bits wide.
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CY82C693UB