CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 37

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

CY82C693UB Control Registers
The control registers for the CY82C693UB are defined in this
section. The registers can be accessed through I/O Ports 22H
and 23H (PCI I/O Reads or Writes to address 22H and 23H).
To access each register, the user must first write the index
Register 1: Peripheral Configuration Register #1 (Read/Write) — Index=01H
Bit
7:6
5:4
3:2
1
0
Function
I/O Wait State Control:
00:
01:
10:
11:
This register field is used to aid in ISA compatibility. ISA cards that cannot respond fast
enough may require wait states to be inserted into each ISA cycle. Wait states are inserted
by the deassertion of the IOCHRDY signal. IOCHRDY will remain deasserted for the number
of wait states (AT clock cycles) programmed into this register field.
16-bit DMA Wait State Control
00:
01:
10:
11:
This bit field allows wait state control on 16-bit accesses. Wait states are inserted by the
deassertion of the IOCHRDY signal. IOCHRDY will remain deasserted for the number of wait
states (AT clock cycles) programmed into this register field.
8-bit DMA Wait State Control
00:
01:
10:
11:
This bit field allows wait state control on 8-bit accesses. Wait states are inserted by the
deassertion of the IOCHRDY signal. IOCHRDY will remain deasserted for the number of wait
states (AT clock cycles) programmed into this register field.
MEMR Leading Edge Delay Control:
0:
1:
This bit allows the assertion of the MEMR signal to be delayed during DMA transactions.
Normally MEMR is asserted one DMA clock cycle later than IOR during DMA. This delay may
be removed so that MEMR and IOR are asserted at the same time.
DMA Controller Clock Speed Control:
0:
1:
This bit allows the clock that controls the DMA controllers to be sped by running directly off
of the ATCLK. Normally, the DMA clock is the AT clock divided by two. When this bit changes,
internal synchronization logic prevents short clock pulses.
1 Wait State
2 Wait States
3 Wait States
4 Wait States
1 Wait State
2 Wait States
3 Wait States
4 Wait States
1 Wait State
2 Wait States
3 Wait States
4 Wait States
1 DMA clock delay
No delay
DMA clock is ATCLK divided by two
DMA clock is ATCLK
PRELIMINARY
37
number of the register into Port 22, which forces the internal
decoding logic to point to the selected register. Data can be
accessed by then reading/writing to/from Port 23.
-
.
CY82C693UB
Default
11
00
00
0
0