CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 75

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

Command Register Format (Write Only)
DMA Register 9: DMAC1 DMA Request Register (Write Only) - I/O Address=009H
DMA Request Register Write Format. (This Register is used to generate DMA requests through software. Multiple Software
requests can be generated with separate writes to this register. Software DMA Requests cannot be masked.
Bit
7
6
5
4
3
2
1
0
I/O Read I/O Write Flip-Flop State Function
Bit
7:3
2
1:0
0
1
1
0
Function
DMA Acknowledge Signal Active Level Control:
0:
1:
DMA Request Signal Active Level Control:
0:
1:
Reserved, Must be 0
DMA Priority Control:
0:
1:
DMA Compressed Timing Control:
0:
1:
Normal DMA word transfers take 4 DMA clock cycles. Compressed timing causes the com-
mand signals and the terminal count signal to be asserted one cycle earlier. This allows the
entire DMA transfer to be compressed to 3 DMA clock cycles.
DMA Controller Disable Control:
0:
1:
Disabling the DMA Controllers prevents DMA cycles from occurring during channel program-
ming.
Address Hold Control:
0:
1:
Memory to Memory Transfer Control:
0:
1:
Function
Reserved
DMA Request Generation Control:
0:
1:
DMA Request Channel Selector:
00:
01:
10:
11:
DACK signals are active LOW
DACK signals are active HIGH
DREQ signals are active HIGH
DREQ signals are active LOW
DMA Requests will be honored according to fixed priority (Channel 0 has highest
priority/Channel 7 has lowest priority)
DMA Requests will be honored according to rotating priority (Every time a channel
is acknowledged, it rotates to lowest priority)
Disable Compressed Timing
Enable Compressed Timing
Normal Operation
Disable DMA Controllers
Normal Operation
Force the value in Channel 0’s Current Address Register to remain the same
(no increment or decrement). Used for memory to memory transfers.
Normal Operation
Channel 0 and channel 1 will be used for memory to memory transfers.
X
X
Do not generate a DMA Request
Force a DMA Request on the channel specified by bits[1:0].
Channel 0
Channel 1
Channel 2
Channel 3
Undefined
Write DMA Request Register
PRELIMINARY
75
CY82C693UB
Default
0
0
0
0
0
0
0
0
Default
00000
0
00