CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 87

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

CY82C693UB IDE (Bus Mastering) DMA
Controller Registers
The CY82C693UB supports two channels of DMA for the IDE
controller. IDE DMA is compatible with SFF-8038i (the Small
Form Factor Committee specification defining bus mastering
on IDE). Only 16-bit DMA operation is supported.
The IDE DMA controller supports scatter-gather. Scatter-gath-
er operation requires setting up a linked list of DMA information
in memory (Physical Region Descriptor Table) and program-
SFF-8038i Registers
Bus Master IDE Command Register Format (Offset+00H for Primary Channel; Offset +08H for Secondary Channel)
Offset from
Base Address Register
00H
01H
02H
03H
04H-07H
08H
09H
0AH
0BH
0CH-0FH
Bit
7:4
3
2:1
0
Bus Master IDE Command Register (Primary Channel)
Reserved
Bus Master IDE Status Register (Primary Channel)
Reserved
Bus Master IDE Descriptor Table Pointer Register (Primary Channel)
Bus Master IDE Command Register (Secondary Channel)
Reserved
Bus Master IDE Status Register (Secondary Channel)
Reserved
Bus Master IDE Descriptor Table Pointer Register (Secondary Channel)
Function
Reserved
Bus Master (DMA) Transfer Direction:
0:
1:
NOTE: This bit must NOT be changed when the bus master function is active.
Reserved
Start/Stop Bus Master Transfer:
Bus Master operation begins when this bit is written from a 0 to a 1. The controller will transfer
data between the IDE device and memory when this bit is set. Master operation can be halted
by writing a 0 to this bit. All state information is lost when a master operation is halted.
Therefore, master operations cannot be halted and then resumed.
PCI bus master read.
PCI bus master write.
PRELIMINARY
87
ming the starting location of the linked-list into the DMA con-
troller itself. The controller will issue master cycles on PCI to
gather and load the DMA information (word count and starting
address). After each DMA terminal count is reached, the next
entry in the linked-list is loaded until the end of the list is
reached.
Some DMA IDE Registers are referenced to a Base Address
+ an offset. The base address should be programmed in PCI
configuration space (see the “Bus Master IDE I/O Base Ad-
dress Register”).
CY82C693UB
R/W
Readable/
Writable
Do not access
Readable/
Writable-
Writing a 1
clears the cor-
responding bit.
Do not access
Readable/
Writable
Readable/
Writable
Do not access
Readable/
Writable-
Writing a 1
clears the cor-
responding bit.
Do not access
Readable/
Writable
Default
0000
0
00
0