CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 89

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CY82C693UB

Manufacturer Part Number
CY82C693UB
Description
Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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hyperCache Specific (Not Required by SFF-8038i) Registers
The following registers define options/functions that are not explicitly covered by the SFF-8038i spec. Nonetheless, these registers
should be programmed for complete operation.
Bus Master IDE Channel 0 Configuration Register (I/O Address 22H with Data = 30 (Index Port); I/O Address 23H is the
Data Port)
Bus Master IDE Channel 1 Configuration Register (I/O Address 22H with Data = 31 (Index Port); I/O Address 23H is the
Data Port)
Bus Master IDE TimeOut Register (I/O Address 22H with Data = 32 (Index Port); I/O Address 23H is the Data Port) - Write
Only
Bus Master IDE Test Register (I/O Address 22H with Data = 33 (Index Port); I/O Address 23H is the Data Port)
Bit
7:3
2
1:0
Bit
7:3
2
1:0
Bit
7:0
Bit
7:0
Function
Reserved. Will Return ’00000’ on read.
IDE DMA Transfer Mode:
0:
1:
IDE DMA Transfer Speed Mode:
00:
01:
10:
11:
Function
Reserved. Will Return ’00000’ on read.
IDE DMA Transfer Mode:
0:
1:
IDE DMA Transfer Speed Mode:
00:
01:
10:
11:
Function
IDE DMA time out counter value.
This register provides the terminal count on a counter with a 14.318 MHz clock input.
Therefore, to find the timeout period, multiply the value in this register by 69.8 ns.
Function
Undefined on read; Must write 00000000 on writes to this register.
Multiple
Single
Mode 0
Mode 1
Mode 2
Reserved
Multiple
Single
Mode 0
Mode 1
Mode 2
Reserved
PRELIMINARY
89
CY82C693UB
Default
00000
0
00
Default
00000
0
00
Default
28H
Default
00000000

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