CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 93

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

ICW1: INTC2 Interrupt Initialization Command Word 1 (Write Only) - I/O Address=0A0H
ICW2: INTC2 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=0A1H
ICW3: INTC2 Interrupt Initialization Command Word 3 (Write Only) - I/O Address=0A1H
Bit
7:5
4
3
2
1
0
Bit
7:3
2:0
Bit
7:3
2:0
Function
Reserved, Must be 000
Controller Initialization Control:
0:
1:
Controller Interrupt Request Control:
0:
1:
If this is set to 1, the interrupt requests must remain active until after the Interrupt Acknowl-
edge Cycle to return the proper vector. If the request goes away early, and no other interrupts
are being requested, the vector returned will correspond to IR7. The interrupt request must
be removed before the End-of-Interrupt to insure that a second spurious interrupt will not
occur.
Don’t Care
Controller Cascade Control:
0:
1:
ICW4 Write Status:
0:
1:
Function
Upper 5 bits of the interrupt vector. These will appear on AD[7:3] during the data phase of an
interrupt acknowledge cycle. AD[2:0] are driven with the interrupt level that comes out of the
priority resolution logic (0 through 7).
Interrupt Request Level, Must write to 000.
Function
Reserved (These bits must be set to zero)
This is the slave mode address that the controller will respond to. This should be written to
02H for proper Cascade mode operation with INTC1.
This is an Operational Command Word Write
This is an Initialization Command Word Write (and begins the Initialization
Sequence.)
Edge-Triggered
Level-Sensitive
Cascade Mode (for multiple interrupt controllers)
Single Mode (There are two controllers in the CY82C693UB. Therefore, this bit
should NEVER be programmed to one.)
ICW4 write not required
ICW4 write required.
PRELIMINARY
93
CY82C693UB
Default
000
0
0
0
0
0
Default
00000
000
Default
00000
000