CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 94

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

ICW4: INTC2 Interrupt Initialization Command Word 4 (Write Only) - I/O Address=0A1H
OCW1: INTC1 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=021H
All Mask Bits are cleared by writing ICW1.
Bit
7:5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Function
Don’t Care
Multiple Interrupt Control:
0:
1:
This bit (when set) allows INTC2 to fully nest interrupts, when Cascaded with Fixed Priority,
without being blocked by INTC1. Correct handling requires the CPU to issue non-specific
EOIs to INTC2 and check its ISR when exiting an interrupt service routine. If the ISR contains
zero, a non-specific EOI should be sent to INTC1. If the ISR contains anything other than
zero, no command should be issued to INTC1.
Buffered Mode:
0:
1:
Master/Slave stored in buffer. Must be set to 0.
Automatic End-of-Interrupt (AEOI) Control:
0:
1:
AEOI should not be enabled if the system supports fully nested interrupts unless this con-
troller is a Cascade Master.
Microprocessor Mode:
0:
1:
NOTE: This bit must be set to 1.
Function
IR7 Mask Control:
0:
1:
IR6 Mask Control:
0:
1:
IR5 Mask Control:
0:
1:
IR4 Mask Control:
0:
1:
IR3 Mask Control:
0:
1:
IR2 Mask Control:
0:
1:
IR1 Mask Control:
0:
1:
IR0 Mask Control:
0:
1:
Disable Multiple Interrupts from the Same Channel
Enable Multiple Interrupts from the Same Channel
Not Buffered
Buffered
Disable AEOI
Enable AEOI
Not x86
x86
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
Not Masked
Masked
PRELIMINARY
94
CY82C693UB
Default
000
0
0
0
0
0
Default
0
0
0
0
0
0
0
0