CY82C693UB Cypress Semiconductor Corporation., CY82C693UB Datasheet - Page 97

• Manufacturer Part Number: CY82C693UB
• Description: Hypercache Tm / Stand-alone Pci Peripheral Controller With Usb
• Manufacturer: Cypress Semiconductor Corporation.

OCW3: INTC2 Interrupt Operational Command Word 3 (Write Only) - I/O Address=0A0H
2CY82C693UB
Bit
7
6
5
4
3
2
1:0
Function
Reserved (Must be set to zero)
Set/Reset Special Mask Mode Control:
0:
1:
This bit allows the Special Mask Mode bit (bit 5) to be protected.
When this bit is disabled, bit 5 will not change.
Special Mask Mode Control:
0:
1:
In Special Mask Mode, writing a 1 to any bit position inhibits interrupts on the associated
channel. Writing a 0 to any bit position enables interrupts on the associated channel. The
mask is handled by causing the priority resolution logic to ignore the condition of the ISR.
Controller Initialization Control:
0:
1:
Operational Command Word Selection Control:
0:
1:
Interrupt Polling Control:
0:
1:
In systems where interrupts are polled, writing a 1 to this bit causes an interrupt status word
to be returned on the next I/O read to the controller. Bit 7 of the data will give interrupt pending
status (0 for no interrupts pending, 1 for interrupts pending). The level of the highest pending
interrupt is encoded on bits 2–0. The IRR will not change until the read cycle is completed.
The PM bit will automatically reset.
Status Control:
00:
01:
10:
11:
Disable Set/Reset of Special Mask Mode Bit
Enable Set/Reset of Special Mask Mode Bit
Disable Special Mask Mode
Enable Special Mask Mode
This is an Operational Command Word Write
This is an Initialization Command Word Write (and begins the Initialization
Sequence.)
This is a write to OCW2
This is a write to OCW3
Disable Polling Cycle
Enable Polling Cycle
Disable Status Read
Disable Status Read
Contents of the IRR will be read on a status read.
Contents of the ISR will be read on a status read.
PRELIMINARY
97
CY82C693UB
Default
0
0
0
0
0
0
00