ADL5330 Analog Devices, Inc., ADL5330 Datasheet
ADL5330
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ADL5330 Summary of contents
Page 1
... The output of the high accuracy wideband attenuator is applied to a differential transimpedance output stage. The output stage sets the 50 Ω differential output impedances and drives Pin OPHI and Pin OPLO. The ADL5330 has a power-down function. It can be powered down by a Logic LO input on the ENBL pin. The current consumption in power-down mode is 250 μ ...
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... ADL5330 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 12 Applications..................................................................................... 13 Basic Connections ...................................................................... 13 RF Input/Output Interface ........................................................ 14 REVISION HISTORY 6/05—Rev Rev. A Changes to Figure 1.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 5 Changes to Table 3............................................................................ 6 Changes to Figure 27 ...
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... V (differential output) GAIN Gain = 0 dB, gain = slope (V − intercept) GAIN V = 1.2 V GAIN V = 1.4 V GAIN V = 1.4 V GAIN 20 MHz carrier offset 1.4 V GAIN V = 1.4 V GAIN 1 V < V < 1.4 V GAIN Rev Page ADL5330 Min Typ Max Unit 0.01 3 GHz 50 Ω 50 Ω −35 dB 0.09 dB 20.7 mV/dB 0. ...
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... ADL5330 Parameter 2200 MHz Gain Control Span Maximum Gain Minimum Gain Gain Flatness vs. Frequency Gain Control Slope Gain Control Intercept Input Compression Point Input Compression Point Output Third-Order Intercept (OIP3) 1 Output Noise Floor Noise Figure 2 Input Return Loss Output Return Loss ...
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... V section of this specification is not implied. Exposure to absolute VPS1, VPS2 maximum rating conditions for extended periods may affect 2.5 V device reliability. 1.1 W 60°C/W 150°C −40°C to +85°C −65°C to +150°C 300°C Rev Page ADL5330 ...
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... OPHI 23 ENBL 24 GAIN VPS1 VPS2 1 18 PIN 1 COM1 COM2 2 INDICATOR 17 INHI OPHI 3 16 ADL5330 OPLO INLO 4 15 TOP VIEW COM1 COM2 5 14 (Not to Scale) VPS1 VPS2 6 13 Figure 2. Pin Configuration Descriptions Positive Supply. Nominally equal Common for Input Stage. Differential Inputs, AC-Coupled. ...
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... Figure 7. Gain and Gain Law Conformance vs. V over Temperature at 2700 MHz 180 160 140 120 100 V GAIN 100 1,000 FREQUENCY (kHz) Figure 8. Frequency Response of Gain Control Input, Carrier Frequency = 900 MHz ADL5330 –3 –6 –9 –12 1.2 1.4 GAIN –3 –6 – ...
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... ADL5330 40 OIP3 30 20 INPUT P1dB 10 0 –10 OUTPUT P1dB –20 –30 –40 0 0.2 0.4 0.6 0.8 V (V) GAIN Figure 9. Input Compression Point, Output Compression Point, OIP3, and Noise Floor vs. V GAIN INPUT P1dB 10 0 –10 OUTPUT P1dB –20 –30 –40 0 0.2 0.4 0.6 0.8 V (V) GAIN Figure 10. Input Compression Point, Output Compression Point, OIP3, and Noise Floor vs ...
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... OIP3 (–40°C) OIP3 (+85°C) OP1dB (+85°C) OP1dB (–40°C) OP1dB (+25°C) 0.2 0.4 0.6 0.8 1.0 1.2 V (V) GAIN OIP3 (+85°C) OIP3 (+25°C) OP1dB (+25°C) OP1dB (–40°C) OP1dB (+85°C) 0.2 0.4 0.6 0.8 1.0 1.2 V (V) GAIN TEMP = +85°C TEMP = –40°C 0.2 0.4 0.6 0.8 1.0 1.2 V (V) GAIN Figure 20. Supply Current vs. V and Temperature GAIN ADL5330 1.4 1.4 1.4 ...
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... ADL5330 18.5 19 19.5 20 20.5 21 21.5 22 22.5 OP1dB (dBm) Figure 21. OP1dB Distribution at 900 MHz at Maximum Gain 9.5 10 10.5 11 11.5 12 12.5 13 13.5 OP1dB (dBm) Figure 22. OP1dB Distribution at 2200 MHz at Maximum Gain 28.5 29.5 30.5 31.5 32.5 OIP3 (dBm) Figure 23. OIP3 Distribution at 900 MHz at Maximum Gain ...
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... Figure 30. Output Return Loss with ETC1-1-13 Baluns Rev Page ADL5330 90 60 120 450MHz V = 0.2V GAIN V = 1.2V GAIN 3GHz 1.9GHz 240 300 270 Figure 29. Output Impedance (Differential) 600 1100 ...
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... The outputs of the ADL5330 require external dc bias to the positive supply voltage. This bias is typically supplied through external inductors. The outputs are best taken differentially to ...
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... The nominal input and output impedance looking into each individual RF input/output pin is 25 Ω. Consequently, the differential impedance is 50 Ω. To enable the ADL5330, the ENBL pin must be pulled high. Taking ENBL low puts the ADL5330 in sleep mode, reducing current consumption to 250 μA at ambient. The voltage on ENBL must be greater than 1 ...
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... Figure 33 illustrates differential balance at the input and output using a transformer balun. Input and output baluns are recom- mended for optimal performance. Much of the characterization for the ADL5330 was completed using 1:1 baluns at the input and output for single-ended 50 Ω match. Operation using M/A-COM ETC1-1-13 transmission line transformer baluns is recommended for a broadband interface ...
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... It offers a large detection range with ±0.5 dB tempera- ture stability. This configuration is similar to Figure 36. The gain of the ADL5330 is controlled by the output pin of the AD8318. This voltage, VOUT, has a range near VPOS. To avoid overdrive recovery issues, the AD8318 output voltage can be scaled down using a resistive divider to interface with the ...
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... SIGNAL DAC 220pF Figure 37. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318 Figure 38 shows the transfer function of the output power vs. the VSET voltage over temperature for a 900 MHz sine wave with an input power of −1.5 dBm. Note that the power control of the AD8318 has a negative sense ...
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... MHz carrier offset. A CH1 2.60V Figure 41. AD8349 and ADL5330 Output Power, ACPR, EVM, and Noise vs. The output of the AD8349 driving the ADL5330 should be limited to the range that provides the optimal EVM and ACPR performance. The power range is found by sweeping the output power of the AD8349 to find the best compromise between EVM and ACPR of the system ...
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... ADL5330 WCDMA TRANSMIT APPLICATION Figure 43 shows a plot of the output spectrum of the ADL5330 transmitting a single-carrier WCDMA signal (Test Model 1-64 at 2140 MHz). The carrier power output is approximately −9.6 dBm. The gain control voltage is equal to 1.4 V giving a gain of approximately 14.4 dB. At this power level, an adjacent channel power ratio of − ...
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... MHz, three-carrier CDMA2000 test model signal (forward pilot, sync, paging, and six traffic, as per 3GPP2 C.S0010-B, Table 6.5.2.1) was applied to the ADL5330. A cavity- tuned filter with a 4.6 MHz pass band was used to reduce noise from the signal source being applied to the device. ...
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... Use the INPUT2 SMA to drive one of the differential input pins. The unused pin should be terminated to ground, as shown in Figure 34. The ADL5330 is enabled by applying a logic high voltage to the ENBL pin by placing a jumper across the SW1 header in the O position. Remove the jumper for disable. This pulls the ENBL pin to ground through the 10 kΩ ...
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... VPS2 COM2 VPS2 GNLO VPS2 COM1 VPS2 OPBS ENBL IPBS GAIN VREF Figure 49. Evaluation Board Schematic Rev Page ADL5330 ...
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... C11 and C2 are dc blocks. L3 and L4 provide dc biases for the output. SW1, R1, R13 Enable Interface. The ADL5330 is enabled by applying a logic high voltage to the ENBL pin by placing a jumper across SW1 to the O position. Remove the jumper for disable. To exercise the enable function by applying an external high or low voltage, use the pin labeled O on the SW1 header ...
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... Figure 50. Component Side Silkscreen Figure 51. Circuit Side Silkscreen Figure 52. Component Side Layout Figure 53. Circuit Side Layout Rev Page ADL5330 ...
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... ADL5330ACPZ-WP −40°C to +85°C 1 ADL5330ACPZ-REEL7 −40°C to +85°C 1 ADL5330ACPZ-R2 −40°C to +85°C ADL5330-EVAL Pb-free part waffle pack. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 4.00 BSC SQ ...