HT45R35V Holtek Semiconductor Inc., HT45R35V Datasheet
HT45R35V
Related parts for HT45R35V
HT45R35V Summary of contents
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... Up to 0.5 s instruction cycle with 8MHz system clock at V =5V DD General Description The HT45R35V Type with 8-bit high perfor- mance RISC architecture microcontroller designed es- pecially for VFD applications. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, etc. combine to ensure user applications require a minimum of exter- nal components ...
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... Block Diagram Rev. 1.00 2 HT45R35V January 15, 2009 ...
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... VFD interface pins and not as nor- mal I/O pins. Capacitor or resistor connection pins Capacitor or resistor connection pin to RC OSC Oscillation input pin Reference resistor connection pin Reference capacitor connection pin High voltage filament output signal 3 HT45R35V January 15, 2009 ...
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... Total Power Dissipation .....................................500mW Test Conditions V V Conditions =4MHz SYS f =8MHz SYS 3V No load, f =4MHz SYS 5V No load, f =8MHz 5V SYS 3V No load, system HALT load, system HALT 5V 4 HT45R35V Ta=25 C Min. Typ. Max. Unit 2.2 5.5 V 3.3 5 ...
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... No load, BZI input 50kHz 24V 18V 5V No load, F1 input 50kHz 24V 18V 5V No load 24V 18V 24V 18V 24V 18V 24V 5 HT45R35V Min. Typ. Max. Unit 0. 2.7 3.0 3 ...
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... CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC V =15V CC 6 HT45R35V Min. Typ. Max. Unit TBD TBD mA 2.5 5.0 mA TBD TBD TBD TBD mA Ta=25 C Typ. Max. Unit 4000 kHz 8000 ...
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... A.C. Waveforms Data Propagation Delays, Setup and Hold Times Strobe Propagation Delays, Setup and Hold Times Rev. 1.00 7 HT45R35V January 15, 2009 ...
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... Program Counter S10 Program Counter S10~S0: Stack register bits @7~@0: PCL bits 8 HT45R35V * ...
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... At the end of a subroutine or an interrupt routine, signaled Table Location * Table Location P10~P8: Current program counter bits 9 HT45R35V * January 15, 2009 ...
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... Bit 7 of the memory pointers are not implemented. How- ever, it must be noted that when the memory pointers in this device is read, a value of 1 will be read. 10 HT45R35V January 15, 2009 ...
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... If the contents of the status are important and if the subroutine can cor- rupt the status register, precautions must be taken to save it properly. Function Status (0AH) Register 11 HT45R35V INC, DEC instruction or a system January 15, 2009 ...
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... To return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Function INTC0 (0BH) Register Function INTC1 (1EH) Register 12 HT45R35V January 15, 2009 ...
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... Note and C2 values are for guidance only the crystal manufacturer specified load capacitor value. Crystal Recommended Capacitor Values Resonator C1 and C2 Values Resonator Frequency 3.58MHz 1MHz 455kHz Note: C1 and C2 values are for guidance only. Resonator Recommended Capacitor Values 13 HT45R35V Cb Rf TBD TBD TBD TBD TBD TBD ...
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... WDT oscillator is the recommended choice, since the HALT instruction will stop the system clock. WS2 WS1 WS0 WDTS (09H) Register Watchdog Timer 14 HT45R35V Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 January 15, 2009 ...
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... If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power Down mode. 15 HT45R35V January 15, 2009 ...
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... Input mode Stack Pointer Points to the top of the stack Reset Configuration Reset Circuit Note: Most applications can use the Basic Reset Cir- cuit as shown, however for applications with ex- tensive noise recommended to use the Hi-noise Reset Circuit. 16 HT45R35V m January 15, 2009 ...
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... HT45R35V RES Reset WDT Time-out (HALT) (HALT)* -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu ...
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... The TON bit must be set again by software for further measurements Timer/Event Counter Function =f SYS =f /2 SYS =f /4 SYS =f /8 SYS =f /16 SYS =f /32 SYS =f /64 SYS =f /128 SYS TMRC (0EH) Register 18 HT45R35V clock. The pulse width INT clock source. In the INT January 15, 2009 ...
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... TMRAH/TMRBH obtains the contents of Timer A/Timer B. Writing to TMRAL/TMRBL only writes the data into a low byte buffer. However writing to TMRAH/TMRBH will write the data and the contents of the low byte buffer into Function RCOCCR (22H) Register Function RCOCR (25H) Register 19 HT45R35V January 15, 2009 ...
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... RCOCF; bit 4 of INTC1. The Timer A and Timer B will stop counting and will reset the RCOCON bit the same time. If the RCOCON bit TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written. /4 and timer on SYS 20 HT45R35V January 15, 2009 ...
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... Defines RC12 analog switch off. AS12ON= 3 AS12ON 0=Analog switch 12 on, and RC12 is disconnected to pull-low 1=Analog switch 12 off, and RC12 is connected to pull-low or not according ASPLON5 register 4~7 Unused bit, read as 0 Rev. 1.00 Function ASCR0 (1AH) Register Function ASCR1 (1BH) Register 21 HT45R35V January 15, 2009 ...
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... RC12 are non-pull-low 5 ASPLON5 1=RC11 and RC12 are pull-low or not according RC11, RC12 analog off. RC11/RC12 is connected to pull-low when ASPLON5=1 and AS11ON/AS12ON analog switch is off. 6~7 Unused bit, read as 0 Rev. 1.00 Function ASCR2 (1CH) Register Analog Switch 22 HT45R35V January 15, 2009 ...
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... This VFD driver converts the shift register into VFD panel driving signals and makes the necessary voltage level shifting. The microcontroller will only transmit data to the VFD driver, no data is transmit- ted from the VFD driver to the microcontroller. Input/Output Ports 23 HT45R35V January 15, 2009 ...
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... VFD display and buzzer operation advised that the configuration options se- lect pull-high resistors to be connected to these lines to keep the lines at a fixed high level when power is initially applied and until the lines can be setup as outputs. VFD Driver 24 HT45R35V VFD0 VFDn 0 VFDn-1 1 VFDn-1 ...
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... Since low voltage has to be maintained its original state for longer than t the reset mode. Rev. 1.00 The relationship between the voltage range for proper chip Note: OPR operation at 4MHz system clock. Low Voltage Reset , therefore a t LVR 25 HT45R35V and V is shown below. DD LVR delay enters LVR January 15, 2009 ...
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... Enable or disable X tal mode or RC mode Disable, rising edge, falling edge or double edge Disable, rising edge, falling edge or double edge PA0 or RC1, PA1 or RC2, PA2 or RC3, PA3 or RC4, PA4 or RC9, PA5 or RC10, PA6 or RC11, PA7 or RC12 HT45R35V Description January 15, 2009 ...
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... Application Circuit Application Circuit Note: 1. The *R resistance and *C capacitance should be consideration for the frequency of RC OSC 1~R 12 are the resistance sensors. sensor sensor 3. C 1~C 12 are the capacitance sensors. sensor sensor Rev. 1. HT45R35V January 15, 2009 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 28 HT45R35V January 15, 2009 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 29 HT45R35V Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 30 HT45R35V Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 31 HT45R35V January 15, 2009 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 32 HT45R35V January 15, 2009 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT45R35V January 15, 2009 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 34 HT45R35V January 15, 2009 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 35 HT45R35V January 15, 2009 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 36 HT45R35V January 15, 2009 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT45R35V January 15, 2009 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT45R35V January 15, 2009 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 39 HT45R35V January 15, 2009 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 40 HT45R35V January 15, 2009 ...
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... Package Information 52-pin QFP (14mm´14mm) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 17.3 13.9 17.3 13.9 1 0.4 2.5 0.1 0.73 0 HT45R35V Max. 17.5 14.1 17.5 14.1 3.1 3.4 1.03 0.2 7 January 15, 2009 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 42 HT45R35V January 15, 2009 ...