HT46R62 Holtek Semiconductor Inc., HT46R62 Datasheet
HT46R62
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HT46R62 Summary of contents
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... A/D product applications that interface di- rectly to analog signals and which require LCD Inter- face. The mask version HT46C62 is fully pin and functionally compatible with the OTP version HT46R62 device. The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, multi-channel A/D Rev ...
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... Block Diagram Rev. 1.70 HT46R62/HT46C62 2 February 14, 2006 ...
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... Pin Assignment Note: The 52-pin QFP package does not support the charge pump (C type bias) of the LCD. The LCD bias type must select the R type by option. Rev. 1.70 HT46R62/HT46C62 3 February 14, 2006 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.70 HT46R62/HT46C62 Description +6.0V Storage Temperature ............................ 125 ...
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... IH2 V Low Voltage Reset Voltage LVR V Low Voltage Detector Voltage LVD I/O Port Segment Logic Output I OL1 Sink Current I/O Port Segment Logic Output I OH1 Source Current Rev. 1.70 HT46R62/HT46C62 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V No load, ADC Off, f =4MHz ...
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... System Start-up Timer Period SST t Low Voltage Width to Reset LVR t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note 1/f SYS SYS Rev. 1.70 HT46R62/HT46C62 Test Conditions Min. V Conditions DD 3V 210 V =0. 350 =0. 180 3V ...
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... Return From Subroutine S10 Note: *10~*0: Program counter bits #10~#0: Instruction code bits Rev. 1.70 HT46R62/HT46C62 specify a maximum of 2048 addresses. After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. ...
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... Note: *10~*0: Table location bits @7~@0: Table pointer bits Rev. 1.70 HT46R62/HT46C62 · Location 008H Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H. ...
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... All of the data mem- ory areas can handle arithmetic, logic, increment, Rev. 1.70 HT46R62/HT46C62 decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer regis- ters (MP0 ...
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... WDT time-out Unused bit, read as 0 Rev. 1.70 HT46R62/HT46C62 Status Register - STATUS The status register (0AH bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO) ...
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... RTF Real time clock request flag (1=active; 0=inactive) 7 Unused bit, read as 0 Rev. 1.70 HT46R62/HT46C62 tion 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter interrupt is initialized by setting the Timer/Event Counter interrupt request flag (TF ...
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... The 32768Hz crystal oscillator still runs at HALT mode. If the 32768Hz crystal Rev. 1.70 HT46R62/HT46C62 oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. Since the 32768Hz oscillator is also designed ...
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... WDT; otherwise, the WDT may reset the chip due to time-out. Multi-function Timer The HT46R62/HT46C62 provides a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i ...
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... After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power- executing the CLR WDT in- Rev. 1.70 HT46R62/HT46C62 Real Time Clock struction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out oc- ...
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... Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart Rev. 1.70 HT46R62/HT46C62 Reset Configuration Timer/Event Counter One timer/event counters (TMR) are implemented in the microcontroller. The Timer/Event Counter contains a 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source ...
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... ADCR 0100 0000 0100 0000 ACSR 1--- --00 1--- --00 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.70 HT46R62/HT46C62 RES Reset RES Reset WDT Time-out (Normal Operation) (HALT) 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 0000 0000 0000 0000 ...
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... TM1 11= Pulse Width measurement mode (External clock) 00= Unused Rev. 1.70 HT46R62/HT46C62 to ETI disables the related interrupt service. When the PFD function is selected, executing SET [PA].3 in- struction to enable PFD output and executing CLR [PA].3 instruction to disable PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also re- loads that data to the timer/event counter ...
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... CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Rev. 1.70 HT46R62/HT46C62 Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, there s none ...
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... M is 256 for PFD N is preload value for timer/event counter f is input clock frequency for timer/event TMR counter Rev. 1.70 HT46R62/HT46C62 Input/Output Ports PWM The microcontroller provides 3 channels (6+2)/(7+1) (dependent on options) bits PWM output shared with PD0/PD1/PD2. The PWM channels have their data reg- O/P ...
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... Parameter AC (0~1) Duty Cycle i<AC Modulation cycle i (i=0~ Rev. 1.70 HT46R62/HT46C62 The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. PWM Modulation Frequency f /64 for (6+2) bits mode SYS f /128 for (7+1) bits mode ...
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... EOCB flag may have an undefined condition. See Important note for A/D initialization . 7 START Starts the A/D conversion start Reset A/D converter and set EOCB Rev. 1.70 HT46R62/HT46C62 converter circuit is powered-on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter ...
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... ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRH ; read conversion result high byte value from the ADRH register mov adrh_buffer,a ; save result to user defined memory Rev. 1.70 HT46R62/HT46C62 PB5 PB4 PB3 PB2 PB5 ...
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... The figure illus- trates the mapping between the display memory and LCD pattern for the device. Display Memory Rev. 1.70 HT46R62/HT46C62 A/D Conversion Timing LCD Driver Output The output number of the device LCD driver can option (i.e., 1/2 duty, 1/3 duty or 1/4 duty) ...
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... LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type) Rev. 1.70 HT46R62/HT46C62 24 February 14, 2006 ...
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... SEG0~SEG7 is together byte optioned as logical output, SEG8~SEG15 are bit individually optioned as logical outputs. LCD Type R Type LCD Bias Type 1/2 bias 1/3 bias If V >V , then V DD LCD MAX V MAX else V connect to V MAX LCD Rev. 1.70 HT46R62/HT46C62 LCD Driver Output C Type 1/2 bias 1/3 bias > then V connect to V DD, DD LCD 2 else V connect to V1 MAX 25 ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.70 HT46R62/HT46C62 Function RTCC (09H) Register The relationship between V and V ...
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... If PA3 is set as PFD output, PFD is the timer overflow signal of the Timer/Event Counter respectively. PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output PD2: level output or PWM2 output INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low. Rev. 1.70 HT46R62/HT46C62 Options ...
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... VMAX connect to VDD or VLCD or V1 refer to the table. LCD Type R Type LCD bias type 1/2 bias 1/3 bias If V >V , then VMAX connect LCD VMAX else VMAX connect to V Rev. 1.70 HT46R62/HT46C62 C1 0pF 10k 10pF 12k 0pF 10k 25pF 10k 25pF 10k 35pF ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.70 HT46R62/HT46C62 Instruction Description 29 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.70 HT46R62/HT46C62 Instruction Description 30 Flag Cycle Affected 2 None (2) 1 ...
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... Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 addr ...
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... PDF 0* 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 Program Counter addr OV Z ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 Program Counter+1 OV ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 Stack Stack ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ([m]+1) ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1.70 HT46R62/HT46C62 ...
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... Package Information 52-pin QFP (14´14) Outline Dimensions Symbol Min. A 17.3 B 13.9 C 17 0.73 K 0.1 0 Rev. 1.70 HT46R62/HT46C62 Dimensions in mm Nom. Max. 17.5 14.1 17.5 14.1 1 0.4 3.1 3.4 0.1 1.03 0 February 14, 2006 ...
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... SSOP (300mil) Outline Dimensions Symbol Min. A 395 B 291 C 8 720 Rev. 1.70 HT46R62/HT46C62 Dimensions in mil Nom. Max. 420 299 12 730 February 14, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.70 HT46R62/HT46C62 46 February 14, 2006 ...