HT46R64 Holtek Semiconductor Inc., HT46R64 Datasheet

Page 1

... A/D product applications that interface di- rectly to analog signals and which require LCD Inter- face. The mask version HT46C64 is fully pin and functionally compatible with the OTP version HT46R64 device. The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, multi-channel A/D Rev ...

Page 2

... Block Diagram Rev. 1.80 HT46R64/HT46C64 2 February 14, 2006 ...

Page 3

... Pin Assignment Note: The 52-pin QFP package does not support the charge pump (C type bias) of the LCD. The LCD bias type must select the R type by option. Rev. 1.80 HT46R64/HT46C64 3 February 14, 2006 ...

Page 4

... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.80 HT46R64/HT46C64 Description +6.0V Storage Temperature ............................ 125 ...

Page 5

... IH2 V Low Voltage Reset Voltage LVR V Low Voltage Detector Voltage LVD I/O Port Segment Logic Output I OL1 Sink Current I/O Port Segment Logic Output I OH1 Source Current Rev. 1.80 HT46R64/HT46C64 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V No load, ADC Off, f =4MHz ...

Page 6

... System Start-up Timer Period SST t Low Voltage Width to Reset LVR t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note 1/f SYS SYS Rev. 1.80 HT46R64/HT46C64 Test Conditions Min. V Conditions DD 3V 210 V =0. 350 =0. 180 3V ...

Page 7

... S10 Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.80 HT46R64/HT46C64 After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ...

Page 8

... Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 1.80 HT46R64/HT46C64 · Location 008H Location 008H is reserved for the external interrupt service program also. If the INT1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008H. ...

Page 9

... PDC;19H). The remaining space before the 40H is re- served for future expanded usage and reading these lo- cations will get ²00H². The space before 40H is Rev. 1.80 HT46R64/HT46C64 RAM Mapping overlapping in each bank. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands ...

Page 10

... TO is set by a WDT time-out. 6~7 Unused bit, read as 0 Rev. 1.80 HT46R64/HT46C64 Status Register - STATUS The status register (0AH bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a watchdog time-out flag (TO) ...

Page 11

... Time base request flag (1=active; 0=inactive) 6 RTF Real time clock request flag (1=active; 0=inactive) Rev. 1.80 HT46R64/HT46C64 call to location 04H or 08H occurs. The interrupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other maskable interrupts. The internal Timer/Event Counter 0 interrupt is initial- ized by setting the Timer/Event Counter 0 interrupt re- quest flag (T0F ...

Page 12

... For applications where precise RTC frequencies are essential, these components may be re- quired to provide frequency compensation due to different crystal manufacturing tolerances. Rev. 1.80 HT46R64/HT46C64 It is recommended that a program should not use the CALL subroutine within the interrupt subroutine be- ...

Page 13

... WDT; otherwise, the WDT may reset the chip due to time-out. Multi-function Timer The HT46R64/HT46C64 provides a multi-function timer for the WDT, time base and RTC but with different time-out periods. The multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the WDT OSC or RTC OSC or the instruction clock (i ...

Page 14

... The WDT is cleared and start recounting (if the WDT clock source is from the WDT oscillator or the real time clock oscillator). All I/O ports maintain their original status. Rev. 1.80 HT46R64/HT46C64 Time Base The PDF flag is set but the TO flag is cleared. LCD driver is still running (if the WDT OSC or RTC OSC is selected). ...

Page 15

... WDT starts counting Timer/event Counter Off Input/output Ports Input mode Stack Pointer Points to the top of the stack Rev. 1.80 HT46R64/HT46C64 Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart Reset Configuration ...

Page 16

... ADCR 0100 0000 0100 0000 ACSR 1--- --00 1--- --00 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.80 HT46R64/HT46C64 RES Reset RES Reset WDT Time-out (Normal Operation) (HALT) xxxx xxxx xxxx xxxx 00-0 1000 00-0 1000 xxxx xxxx xxxx xxxx ...

Page 17

... Counter 1; TMR1H (0FH), TMR1L (10H) and TMR1C (11H). Writing TMR1L will only put the written data to an Rev. 1.80 HT46R64/HT46C64 internal lower-order byte buffer (8-bit) and writing TMR1H will transfer the specified data and the contents of the lower-order byte buffer to TMR1H and TMR1L registers, respectively ...

Page 18

... T1M1 11=Pulse Width measurement mode (External clock) 00=Unused Rev. 1.80 HT46R64/HT46C64 sult remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will re-function as long as it receives further transient pulse. ...

Page 19

... T2 rising edge of instruction MOV A,[m] (m=12H, 14H Rev. 1.80 HT46R64/HT46C64 or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration ...

Page 20

... PD0/PD1/PD2/PD3 is operating in output mode). Writ- ing 1 to PD0~PD3 data register will enable the PWM Rev. 1.80 HT46R64/HT46C64 Input/Output Ports output function and writing 0 will force the PD0~PD3 to remain The I/O functions of PD0/PD1/PD2/PD3 are as shown ...

Page 21

... A (6+2) bits mode PWM cycle is divided into four modu- lation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. Rev. 1.80 HT46R64/HT46C64 In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM ...

Page 22

... EOCB bit is cleared. The ACSR is A/D clock setting register, which is used to select the A/D clock source. Rev. 1.80 HT46R64/HT46C64 The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. There are a total of eight channels to select. The bit5~bit3 of the ADCR are used to set PB configurations ...

Page 23

... Analog Input Channel Selection Register Bit7 Bit6 ADRL D1 D0 ADRH D9 D8 Note: D0~D9 is A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register Rev. 1.80 HT46R64/HT46C64 Function ADCR (26H) Register PB6 PB5 PB4 PB3 PB2 PB6 PB5 PB4 PB3 ...

Page 24

... ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Rev. 1.80 HT46R64/HT46C64 /8 as the A/D clock SYS A/D Conversion Timing 24 February 14, 2006 ...

Page 25

... LCD Driver Output The output number of the device LCD driver can option (i.e., 1/2 duty, 1/3 duty or 1/4 Rev. 1.80 HT46R64/HT46C64 Display Memory duty). The bias type LCD driver can be R type or C type. If the R bias type is selected, no external capaci- tor is required. If the C bias type is selected, a capaci- tor mounted between C1 and C2 pins is needed ...

Page 26

... LCD Type R Type LCD Bias Type 1/2 bias 1/3 bias If V >V , then V DD LCD V MAX else V connect to V MAX Rev. 1.80 HT46R64/HT46C64 Option High Bias Current (Typ.) (VLCD/4. (VLCD/ ²R² Type Bias Current C Type 1/2 bias 1/3 bias > then V connect to V MAX ...

Page 27

... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.80 HT46R64/HT46C64 Function RTCC (09H) Register The relationship between V and V ...

Page 28

... PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output INT0 or INT1 trigger edge selection: disable; high to low; low to high; low to high or high to low LCD bias current selection: low/high driving current (for R type only). Rev. 1.80 HT46R64/HT46C64 Options ...

Page 29

... VMAX connect to VDD or VLCD or V1 refer to the table. LCD Type R Type LCD bias type 1/2 bias 1/3 bias If V >V , then VMAX connect LCD VMAX else VMAX connect to V Rev. 1.80 HT46R64/HT46C64 C1 0pF 10k 10pF 12k 0pF 10k 25pF 10k 25pF 10k 35pF ...

Page 30

... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.80 HT46R64/HT46C64 Instruction Description 30 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...

Page 31

... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.80 HT46R64/HT46C64 Instruction Description 31 Flag Cycle Affected 2 None (2) 1 ...

Page 32

... Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ...

Page 33

... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 addr ...

Page 34

... PDF 0* 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ...

Page 35

... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...

Page 36

... Operation Program Counter Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 Program Counter addr OV Z ...

Page 37

... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 Program Counter+1 OV ...

Page 38

... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 Stack Stack ...

Page 39

... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ...

Page 40

... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ...

Page 41

... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ([m]+1) ...

Page 42

... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ...

Page 43

... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ...

Page 44

... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1.80 HT46R64/HT46C64 ...

Page 45

... Package Information 52-pin QFP (14´14) Outline Dimensions Symbol Min. A 17.3 B 13.9 C 17 0.73 K 0.1 0 Rev. 1.80 HT46R64/HT46C64 Dimensions in mm Nom. Max. 17.5 14.1 17.5 14.1 1 0.4 3.1 3.4 0.1 1.03 0 February 14, 2006 ...

Page 46

... SSOP (300mil) Outline Dimensions Symbol Min. A 395 B 291 720 Rev. 1.80 HT46R64/HT46C64 Dimensions in mil Nom. Max. 420 299 12 730 February 14, 2006 ...

Page 47

... QFP (14´20) Outline Dimensions Symbol Min. A 18.50 B 13.90 C 24.50 D 19. 2. 0.10 0 Rev. 1.80 HT46R64/HT46C64 Dimensions in mm Nom. Max. 19.20 14.10 25.20 20.10 0.65 0.30 3.10 3.40 0.10 1.40 0. February 14, 2006 ...

Page 48

... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.80 HT46R64/HT46C64 48 February 14, 2006 ...