DSPIC30F2012 Microchip Technology Inc., DSPIC30F2012 Datasheet
DSPIC30F2012
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DSPIC30F2012 Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70139E ...
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... MCUs microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. , microID, MPLAB, PIC, PIC, PICSTART, ® code hopping devices, Serial EEPROMs, OQ © 2006 Microchip Technology Inc. ® ...
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... High-current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • 16-bit Capture input functions © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • 16-bit Compare/PWM output functions • 3-wire SPI modules (supports four Frame modes) 2 • ...
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... Sensor Family Program Memory Device Pins Bytes Instructions dsPIC30F2011 18 12K 4K dsPIC30F3012 18 24K 8K dsPIC30F2012 28 12K 4K dsPIC30F3013 28 24K 8K Pin Diagrams 18-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SPDIP and SOIC ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F2011 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 7 15 DS70139E-page 3 ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70139E-page AN8/OC1/RB8 2 20 AN9/OC2/RB9 3 CN17/RF4 19 dsPIC30F2012 4 CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 7 15 © 2006 Microchip Technology Inc. ...
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... Pin Diagram 44-Pin QFN PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F3012 ...
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... Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70139E-page dsPIC30F3013 OSC2/CLKO/RC15 OSC1/CLKI AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 © 2006 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139E-page 7 ...
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... NOTES: DS70139E-page 8 © 2006 Microchip Technology Inc. ...
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... The following block diagrams depict the architecture for these devices: • Figure 1-1 illustrates the dsPIC30F2011 • Figure 1-2 illustrates the dsPIC30F2012 • Figure 1-3 illustrates the dsPIC30F3012 • Figure 1-4 illustrates the dsPIC30F3013 Following the block diagrams, Table 1-1 relates the I/O functions to pinout information. ...
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... W Reg Array Decode PORTC 16 16 DSP Divide Engine Unit ALU<16> PORTD Input Output 2 Compare I C™ Module SPI1 UART1 EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 © 2006 Microchip Technology Inc. ...
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... FIGURE 1-2: dsPIC30F2012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (12 Kbytes) Data Latch 16 ROM Latch 24 16 Instruction Decode & Control Power-up Timer Timing ...
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... W Reg Array Decode PORTC 16 16 DSP Divide Engine Unit ALU<16> PORTD Input Output 2 Compare I C™ Module Timers SPI1 UART1 EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 © 2006 Microchip Technology Inc. ...
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... Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (1 Kbytes) (1 Kbytes) 16 Address Address Latch ...
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... PORTB is a bidirectional I/O port. ST PORTC is a bidirectional I/O port. ST PORTD is a bidirectional I/O port. ST PORTF is a bidirectional I/O port. ST Synchronous serial clock input/output for SPI1. ST SPI1 Data In. — SPI1 Data Out. ST SPI1 Slave Synchronization. Analog = Analog input O = Output P = Power Description © 2006 Microchip Technology Inc. ...
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... I REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Buffer Type ST Synchronous serial clock input/output for I ST Synchronous serial data input/output for I — 32 kHz low-power oscillator crystal output. ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode ...
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... PIC30F2011/2012/3012/3013 ds NOTES: DS70139E-page 16 © 2006 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes and most instructions can address data either as words or bytes. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Two ways to access data in program memory are: • The upper 32 Kbytes of data space memory can ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. © 2006 Microchip Technology Inc. ...
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... ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM ...
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... DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 © 2006 Microchip Technology Inc. ...
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... ED EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... PIC30F2011/2012/3012/3013 ds FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70139E-page 22 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2006 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...
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... Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2006 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... PIC30F2011/2012/3012/3013 ds NOTES: DS70139E-page 26 © 2006 Microchip Technology Inc. ...
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... The program space memory map for the dsPI30F2011/ 2012 is shown in Figure 3-1. The program space memory map for the dsPI30F3012/3013 is shown in Figure 3-2. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program memory is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1 ...
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... Program Memory (8K instructions) 003FFE 004000 Reserved (Read ‘0’s) 7FFBFE 7FFC00 Data EEPROM (1 Kbyte) 7FFFFE 800000 Reserved 8005BE 8005C0 UNITID (32 instr.) 8005FE 800600 Reserved F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FEFFFE FF0000 DEVID (2) FFFFFE © 2006 Microchip Technology Inc. ...
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... Using Program 0 Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA ...
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... P<23:16> maps to the destination byte when byte select = 0; The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to Section 5.0 “Flash Program Memory” for details on Flash Programming TBLRDL.B (Wn<0> TBLRDL.W TBLRDL.B (Wn<0> © 2006 Microchip Technology Inc. ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for details on instruction encoding. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn< ...
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... W0 ; Access program memory location ; using a data space access Note 1: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address. DS70139E-page 32 Program Space 0x0000 (1) PSVPAG 0x00 8 0x8000 23 15 Address Concatenation 15 23 0xFFFF 0x000000 0 0x001200 0x001FFF Data Read © 2006 Microchip Technology Inc. ...
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... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in Figure 3-7. The data space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in Figure 3-8. 16 bits MSB ...
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... Optionally Mapped into Program Memory 0xFFFF DS70139E-page 34 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2006 Microchip Technology Inc. ...
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... FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 ...
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... FIGURE 3-10: MSB 15 0001 Byte 1 Byte 3 0003 0x0000 Byte 5 0x0000 0005 0x0000 ® DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2006 Microchip Technology Inc. ...
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... Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word aligned ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70139E-page 40 © 2006 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buff- ers that have a power-of-2 length. As these buffers sat- isfy the Start and end address criteria, they can operate in a Bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries). © 2006 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister, MODCON<15:0>, contains enable flags as well register field to specify the W address registers. ...
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... If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be immediately followed Bit-Reversed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled Bit-Reversed Addressing © 2006 Microchip Technology Inc. ...
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... BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer ...
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... NOTES: DS70139E-page 46 © 2006 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 5.6 DD “Programming Operations” for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2006 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2006 Microchip Technology Inc. ...
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TABLE 5-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70139E-page 52 © 2006 Microchip Technology Inc. ...
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... EEPROM write/erase operation. Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2006 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. © 2006 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Any bit and its associated data and Control registers that are not valid for a particular device are disabled. That means the corresponding LATx and TRISx registers and the port pin read as zeros. ...
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... Typically this instruction would be a NOP EXAMPLE 7-1: MOV #0xF0, W0; Configure PORTB<7:4> MOV W0, TRISB; and PORTB<3:0> as outputs NOP btss PORTB, #7; bit test RB7 and skip if set PORT WRITE/READ EXAMPLE ; as inputs ; additional instruction cycle © 2006 Microchip Technology Inc. ...
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... PORTB 02C8 — — — — LATB 02CB — — — — TABLE 7-2: PORTB REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — ...
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... PORTD 02D4 — — — — LATD 02D6 — — — — TABLE 7-6: PORTF REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name TRISF 02DE — — — — PORTF 02E0 — — ...
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... CNEN1 00C0 CN7IE CN6IE CNEN2 00C2 — — CNPU1 00C4 CN7PUE CN6PUE CNPU2 00C6 — — TABLE 7-8: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2012/3013 (BITS 7-0) SFR Addr. Bit 7 Bit 6 Name CNEN1 00C0 CN7IE CN6IE CNEN2 00C2 — — CNPU1 00C4 CN7PUE ...
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... NOTES: DS70139E-page 62 © 2006 Microchip Technology Inc. ...
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... The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers ...
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... U2RX* — UART2 Receiver 25 33 U2TX* — UART2 Transmitter 26-41 34-49 Reserved 42 50 LVD — Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority * Only the dsPIC30F3013 has UART2 and the U2RX, U2TX interrupts. These locations are reserved for the dsPIC30F2011/2012/3012. © 2006 Microchip Technology Inc. ...
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... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously causes a Reset. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1 ...
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... The device is automatically Reset in a hard trap conflict condition. The TRAPR Status bit (RCON<15>) is set when the Reset occurs, so that the condition may be detected in software. © 2006 Microchip Technology Inc. ...
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... The processor then loads the priority level for this inter- rupt into the STATUS register. This action disables all lower priority interrupts until the completion of the Interrupt Service Routine. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 8-2: 0x000000 0x000002 ...
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... If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor wakes up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. © 2006 Microchip Technology Inc. ...
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TABLE 8-2: dsPIC30F2011/2012/3012 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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TABLE 8-3: dsPIC30F3013 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time Clock interrupts These operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 32.768 kHz XTAL pF 100K SOSCI dsPIC30FXXXX SOSCO © 2006 Microchip Technology Inc. ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt is generated if enabled ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for ...
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... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers ...
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... T2CON register. DS70139E-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 Q D TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2006 Microchip Technology Inc. ...
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... Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 ...
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... T3IF bit (IFS0<7>) is asserted and an interrupt is generated if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2006 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70139E-page 80 © 2006 Microchip Technology Inc. ...
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... Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channel (1 or 2). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have two capture channels ...
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... Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. © 2006 Microchip Technology Inc. defined as ...
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TABLE 11-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — Legend uninitialized bit Note: Refer ...
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... NOTES: DS70139E-page 84 © 2006 Microchip Technology Inc. ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channel (1 or 2). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... The OCFLT bit (OCxCON<4>) indicates whether a Fault condition has occurred. This state is maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2006 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
Page 90
TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Legend: ...
Page 91
... SDO1 SS & FSYNC Control SS1 SCK1 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • SS1 (active-low slave select). In Master mode operation, SCK1 is a clock output. In Slave mode clock input. A series of eight (8) or sixteen (16) clock pulses shift out bits from the SPI1SR to SDO1 pin and simulta- neously shift in data from SDI1 pin ...
Page 92
... SPI clock cycle. When Frame Synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock. SDO1 SDI1 Serial Input Buffer SDI1 SDO1 MSb Serial Clock SCK1 SCK1 SPI Slave (SPI1BUF) Shift Register (SPI1SR) LSb PROCESSOR 2 © 2006 Microchip Technology Inc. ...
Page 93
... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 13.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPI1STAT< ...
Page 94
TABLE 13-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Note: Refer to “dsPIC30F Family Reference ...
Page 95
... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
Page 96
... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2006 Microchip Technology Inc. ...
Page 97
... SCL, such that SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘ ...
Page 98
... C bus have de-asserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2006 Microchip Technology Inc. ...
Page 99
... When the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 14. Master Support As a master device, six operations are supported: ...
Page 100
... C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle master event Interrupt Service Rou bus is 2 © 2006 Microchip Technology Inc. C ...
Page 101
TABLE 14- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — ...
Page 102
... NOTES: DS70139E-page 100 © 2006 Microchip Technology Inc. ...
Page 103
... Internal Data Bus UTXBRK Data UxTX Parity Note © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • ...
Page 104
... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2006 Microchip Technology Inc. ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.3 Transmitting Data 15.3.1 ...
Page 106
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2006 Microchip Technology Inc. RXB) ...
Page 107
... FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 108
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2006 Microchip Technology Inc. ...
Page 109
TABLE 15-1: UART1 REGISTER MAP FOR dsPIC30F2011/2012/3012/3013 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — ...
Page 110
... NOTES: DS70139E-page 108 © 2006 Microchip Technology Inc. ...
Page 111
... AN6 0111 AN7 1000 AN8 1001 AN9 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...
Page 112
... ADCSSL register is ‘1’, the corre- sponding input is selected. The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. © 2006 Microchip Technology Inc. ...
Page 113
... There are 64 possible options for T EQUATION 16-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “ ...
Page 114
... Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF See Note 0 0.1 F 0.01 F pin. DD © 2006 Microchip Technology Inc. ...
Page 115
... DAC) HOLD Note: C value depends on device package and is not tested. Effect of C PIN © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The following figure shows the timing diagram of the ADC running at 200 ksps. The T tion with the guidelines described above allows a con- version speed of 200 ksps ...
Page 116
... Each of the output formats translates to a 16-bit result on the data bus. d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 © 2006 Microchip Technology Inc. ...
Page 117
... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16.14 Connection Considerations The analog inputs have diodes to V protection. This requires that the analog input be ...
Page 118
TABLE 16-2: A/D CONVERTER REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...
Page 119
... TABLE 16-3: A/D CONVERTER REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ADCBUF4 0288 — — ...
Page 120
... NOTES: DS70139E-page 118 © 2006 Microchip Technology Inc. ...
Page 121
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 122
... Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70139E-page 120 Description (1) . (2) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2006 Microchip Technology Inc. ...
Page 123
... FIGURE 17-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Internal FRC Osc Primary Oscillator Stability Detector Oscillator ...
Page 124
... OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKO 1 1 CLKO OSC2 0 0 (Note (Note (Note © 2006 Microchip Technology Inc. ...
Page 125
... Table 17-4. If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00001’, ‘01010’ or ‘00011’, then a PLL multiplier (respectively) is applied. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7 ...
Page 126
... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2006 Microchip Technology Inc. ...
Page 127
... Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 128
... OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70139E-page 126 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2006 Microchip Technology Inc. ...
Page 129
... The BOR will select the clock source based on the device Configuration bit values (FOS<2:0> and FPR<4:0>). Furthermore Oscillator mode is © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 selected, the BOR will activate the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, then the clock will be held until the LOCK bit (OSCCON< ...
Page 130
... Microchip Technology Inc. ...
Page 131
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.6 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV; ...
Page 132
... For addi- tional information, please refer to the Programming Specifications of the device. Note: If the code protection Configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V © 2006 Microchip Technology Inc. 4.5V. DD ...
Page 133
... Control registers are already configured to enable module operation). Note: In the dsPIC30F2011, dsPIC30F3012 and dsPIC30F2012 devices, the U2MD bit is readable and writable and will be read as ‘1’ when set. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17 ...
Page 134
TABLE 17-7: SYSTEM INTEGRATION REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — COSC<2:0> OSCTUN 0744 — — — — PMD1 0770 — — T3MD ...
Page 135
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 136
... For more details on the instruction set, refer to the Programmer’s Reference Manual. Description {W13, [W13]+=2} {0...15} {0x0000...0x1FFF} {0,1} {0...15} {0...31} {0...255} {0...255} for Byte mode, {0:1023} for Word mode {0...16384} {0...65535} {0...8388608}; LSB must be 0 {-512...511} {-32768...32767} {-16...16} © 2006 Microchip Technology Inc. ...
Page 137
... Y data space prefetch address register for DSP instructions {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Wyd Y data space prefetch destination register for DSP instructions © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0 ...
Page 138
... Branch if Not Zero Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2006 Microchip Technology Inc Status Flags Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV ...
Page 139
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 140
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Prefetch and store accumulator © 2006 Microchip Technology Inc Status Flags Cycles Affected 1 18 N,Z,C, ...
Page 141
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 142
... Wn = byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws © 2006 Microchip Technology Inc Status Flags Cycles Affected N,Z 1 ...
Page 143
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 144
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2006 Microchip Technology Inc. ...
Page 145
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 146
... Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® battery management, SEEVAL © 2006 Microchip Technology Inc. ...
Page 147
... DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (except V and MCLR) (Note 1) .................................... -0. .......................................................................................................... ± > ...................................................................................................± pin, inducing currents greater than 80 mA, may cause latch-up. ...
Page 148
... Notes 44 — °C — °C — °C — °C — °C/W 1 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- © 2006 Microchip Technology Inc. ...
Page 149
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 150
... Industrial +125°C for Extended 0.128 MIPS LPRC ( 512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS © 2006 Microchip Technology Inc. ...
Page 151
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T ...
Page 152
... bus disabled V SM bus enabled 5V PIN PIN DD Pin at high impedance PIN DD Pin at high impedance PIN XT PIN DD and LP Osc mode © 2006 Microchip Technology Inc. ...
Page 153
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 154
... T +85°C for Industrial A -40°C T +125°C for Extended A Typ Max Units Conditions — — V — — V — — V — — V — 2.65 V — 2.86 V — 2.97 V — 3.18 V — 3.50 V — 3.71 V — 3.82 V — 4.03 V — 4.24 V — 4.45 V — 4.77 V — — V © 2006 Microchip Technology Inc. ...
Page 155
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing values not in usable operating range. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 BO15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 156
... Extended A Conditions - +85°C A Using EECON to Read/Write V = Minimum operating MIN voltage Provided no other specifications are violated Row Erase - +85° Minimum operating MIN voltage Provided no other specifications are violated Row Erase Bulk Erase © 2006 Microchip Technology Inc. ...
Page 157
... FIGURE 20-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 — for all pins except OSC2 Pin FIGURE 20-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T Operating voltage V range as described in Section 20.0 “ ...
Page 158
... MHz FRC internal MHz FRC internal w/4x PLL MHz FRC internal w/8x PLL MHz FRC internal w/16x PLL kHz LPRC internal — See parameter OS10 for F value OSC ns See Table 20- See parameter DO31 ns See parameter DO32 ). CY © 2006 Microchip Technology Inc. ...
Page 159
... AC CHARACTERISTICS Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T (1) (2) ...
Page 160
... Instruction Execution Frequency: MIPS = (F cycle]. DS70139E-page 158 (3) (3) MIPS MIPS (2) ( sec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — 1.0 1.0 4.0 0.4 2.5 10.0 = 1/MIPS PLLx)/4 [since there are 4 Q clocks per instruction OSC (3) (3) MIPS MIPS w PLL x8 w PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — © 2006 Microchip Technology Inc. ...
Page 161
... Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift percentages. TABLE 20-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65 Note 1: Change of LPRC frequency as V © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 -40°C T -40°C T Min Typ Max Units (1) — ...
Page 162
... Operating temperature -40° -40° (1)(2)(3) (4) Min Typ Max — — — — — — CY +85°C for Industrial +125°C for Extended Units Conditions ns — ns — ns — ns — . OSC © 2006 Microchip Technology Inc. ...
Page 163
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 20-2 and Table 20-11 for BOR. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SY10 SY13 Note: Refer to Figure 20-3 for load conditions. Standard Operating Conditions: 2.5V to 5.5V ...
Page 164
... Band Gap Stable T +85°C for Industrial A T +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. RCON<13> bit © 2006 Microchip Technology Inc. ...
Page 165
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 166
... N = prescale value (1, 8, 64, 256) 1.5 T — +85°C for Industrial A +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2006 Microchip Technology Inc. ...
Page 167
... ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40° ...
Page 168
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C (1) (2) Min Typ Max — — — — — — T +85°C for Industrial A T +125°C for Extended A Units Conditions ns See Parameter DO32 ns See Parameter DO31 © 2006 Microchip Technology Inc. ...
Page 169
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 170
... Industrial A -40°C T +125°C for Extended A Max Units Conditions — ns — — ns — — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — — ns — — ns — © 2006 Microchip Technology Inc. ...
Page 171
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP10 SP21 SP35 SP20 BIT ...
Page 172
... Industrial A -40°C T +125°C for Extended A Max Units Conditions — ns — — ns — — — — ns See DO32 — ns See DO31 30 ns — — ns — — ns — — ns — — — ns — © 2006 Microchip Technology Inc. ...
Page 173
... X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 20-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP70 SP73 SP35 SP72 SP52 BIT LSb SP30,SP31 BIT LSb IN SP52 SP72 SP73 SP51 DS70139E-page 171 ...
Page 174
... Extended A Max Units Conditions — ns — — ns — — — — ns See parameter DO32 — ns See parameter DO31 30 ns — — ns — — ns — — ns — — — ns — — © 2006 Microchip Technology Inc. ...
Page 175
... FIGURE 20-17: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 20-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 ...
Page 176
... Time the bus must be free before a new — s transmission can start — s 400 pF 2 C)” © 2006 Microchip Technology Inc. ...
Page 177
... SDA and SCL F SCL Fall Time IS21 T : SDA and SCL R SCL Rise Time Note 1: Maximum pin capacitance = 10 pF for all I © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IS11 IS10 IS26 IS25 IS40 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40°C T ...
Page 178
... Only relevant for Repeated Start condition After this period the first clock pulse is generated — — — Time the bus must be free before a new transmission s can start s pF — © 2006 Microchip Technology Inc. ...
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... Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 CA10 CA11 CA20 Standard Operating Conditions: 2.5V to 5.5V ...
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... V = INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH INL SS REFL 0V REFH © 2006 Microchip Technology Inc. ...
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... AD34 ENOB Effective Number of Bits Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external V © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C Min. ...
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... Family Reference Manual”, (DS70046), Section 18. SAMP 3 - Software clears ADCON. SAMP to Start conversion Sampling ends, conversion sequence starts Convert bit 11 Convert bit 10 Convert bit Convert bit One T for end of conversion. AD DS70139E-page 180 AD55 © 2006 Microchip Technology Inc. ...
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... Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) TABLE 20-38: OPERATING TEMPERATURE-40°C ...
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... NOTES: DS70139E-page 182 © 2006 Microchip Technology Inc. ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example dsPIC30F3012 30I/P Example dsPIC30F2011 30I/SO e 0610017 Example dsPIC30F2012 30I/ 0610017 0610017 ) e 3 DS70139E-page 183 ...
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... SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXX XXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70139E-page 184 Example dsPIC30F3013 e 30I/SO 3 0610017 Example 30F2011 30I/ 0610017 Example dsPIC 30F3013 30I/ 0610017 © 2006 Microchip Technology Inc. ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units ...
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... E .394 .407 .420 E1 .291 .295 .299 D .446 .454 .462 h .010 .020 .029 L .016 .033 .050 .009 .011 .012 B .014 .017 .020 MILLIMETERS MIN NOM MAX 18 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.39 7.49 7.59 11.33 11.53 11.73 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.27 0.30 0.36 0.42 0. © 2006 Microchip Technology Inc. ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units ...
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... E .394 .407 .420 E1 .288 .295 .299 D .695 .704 .712 h .010 .020 .029 L .016 .033 .050 .009 .011 .013 B .014 .017 .020 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. © 2006 Microchip Technology Inc. ...
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... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Package is saw singulated 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED PAD E2 E ...
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... PAD NOTE 1 BOTTOM VIEW A A1 Units MILLIMETERS Dimension Limits MIN NOM 44 N 0.65 BSC e A 0.80 0.90 A1 0.00 0.02 0.20 REF A3 8.00 BSC E E2 6.30 6.45 D 8.00 BSC 6.30 6.45 D2 0.25 0. 0.30 0.40 K 0.20 — Microchip Technology Drawing No. C04–103, Sept. 8, 2006 MAX 1.00 0.05 6.80 6.80 0.38 0.50 — © 2006 Microchip Technology Inc. ...
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... Power-Down Current (I ) Specifications PD (see Table 20-7) • I/O pin Input Specifications (see Table 20-8) • BOR voltage limits (see Table 20-11) • Watchdog Timer time-out limits (see Table 20-21) Revision E (December 2006) This revision includes updates to the packaging diagrams. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139E-page 191 ...
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... NOTES: DS70139E-page 192 © 2006 Microchip Technology Inc. ...
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... Sequence Table (16-Entry)......................................... 45 Block Diagrams 12-bit ADC Functional............................................... 109 16-bit Timer1 Module .................................................. 71 16-bit Timer2............................................................... 77 16-bit Timer3............................................................... 77 32-bit Timer2/3............................................................ 76 DSP Engine ................................................................ 22 dsPIC30F2011 ............................................................ 10 dsPIC30F2012 ............................................................ 11 dsPIC30F3013 ............................................................ 13 External Power-on Reset Circuit............................... 127 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 .............................................................................. 94 Input Capture Mode.................................................... 81 Oscillator System...................................................... 121 Output Compare Mode ...
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... Register Map .............................................................. 83 Input Capture Operation During Sleep and Idle Modes...... 82 CPU Idle Mode ........................................................... 82 CPU Sleep Mode ........................................................ 82 Input Capture Timing Requirements................................. 165 Input Change Notification Module....................................... 61 dsPIC30F2012/3013 Register Map (Bits 7-0)............. 61 Instruction Addressing Modes ............................................ 41 File Register Instructions ............................................ 41 Fundamental Modes Supported ................................. 41 MAC Instructions ........................................................ 42 MCU Instructions ........................................................ 41 Move and Accumulator Instructions ...
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... Register Map for dsPIC30F2012/3013 ....................... 59 PORTC Register Map for dsPIC30F2011/2012/3012/3013 ..... 59 PORTD Register Map for dsPIC30F2011/3012 ....................... 59 Register Map for dsPIC30F2012/3013 ....................... 60 PORTF Register Map for dsPIC30F2012/3013 ....................... 60 Power Saving Modes........................................................ 129 Idle............................................................................ 130 Sleep ........................................................................ 129 Sleep and Idle........................................................... 119 Power-Down Current (I Power-up Timer Timing Characteristics .............................................. 161 Timing Requirements ...
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... Timing Diagrams.See Timing Characteristics Timing Requirements A/D Conversion Low-speed ........................................................ 181 Bandgap Start-up Time............................................. 162 Brown-out Reset ....................................................... 161 CAN Module I/O........................................................ 177 CLKOUT and I/O ...................................................... 160 External Clock........................................................... 156 Bus Data (Master Mode) .................................... 174 Bus Data (Slave Mode) ...................................... 175 © 2006 Microchip Technology Inc. ...
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... Wake-up from Sleep ......................................................... 119 Wake-up from Sleep and Idle ............................................. 68 Watchdog Timer Timing Characteristics .............................................. 161 Timing Requirements................................................ 161 Watchdog Timer (WDT) ............................................ 119, 129 Enabling and Disabling ............................................. 129 Operation .................................................................. 129 WWW Address.................................................................. 199 WWW, On-Line Support ....................................................... 7 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139E-page 197 ...
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... DS70139E-page 198 © 2006 Microchip Technology Inc. ...