DSPIC33FJ12MC202 Microchip Technology Inc., DSPIC33FJ12MC202 Datasheet
DSPIC33FJ12MC202
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DSPIC33FJ12MC202 Summary of contents
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... Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Digital Signal Controllers Preliminary DS70265B ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , K L logo, microID, MPLAB, PIC DSCs code hopping ® ® © 2007 Microchip Technology Inc. ...
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... FIFO on each capture • Output Compare ( channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Interrupt Controller: • 5-cycle latency • 118 interrupt vectors • available interrupt sources • ...
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... IrDA encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Packaging: • 20-pin SDIP/SSOP • 28-pin SDIP/SOIC/QFN Note: See the device variant tables for exact peripheral features per device. Preliminary © 2007 Microchip Technology Inc. ...
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... The following pages show their pinout diagrams. dsPIC33FJ12MC201/202 Controller Families Program Flash Device Pins Memory (Kbyte) (Kbyte) dsPIC33FJ12MC201 20 12 dsPIC33FJ12MC202 28 12 Note 1: Only 2 out of 3 timers are remappable. 2: Only PWM fault inputs are remappable. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Remappable Peripherals RAM (1) ...
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... SDIP/SSOP Package Diagram 20-PIN SDIP 20-PIN SSOP PGD2/EMUD2/AN0/V PGC2/EMC2/AN1/V PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 dsPIC33FJ12MC202 28-Pin SDIP/SOIC Package Diagram 28-PIN SDIP 28-PIN SOIC PGD2/EMUD2/AN0/V PGC2/EMUC2/AN1/V PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5/CN27/RB5 DS70265B-page 4 V MCLR ...
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... QFN Package Diagram 28-Pin QFN 6x6 mm PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 V SS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 PWM1L2/RP13/CN13/RB13 1 21 PWM1H2/RP12/CN14/RB12 TMS/PWM1L3/RP11/CN15/RB11 dsPIC33FJ12MC202 4 18 TDI/PWM1H3/RP10/CN16/RB10 DDCORE TDO/PWM2L1/SDA1/RP9/CN21/RB9 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70265B-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... Family Reference chapters. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 This document contains device specific information for the dsPIC33FJ12MC201/202 Digital Signal Controller (DSC) Devices. The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture ...
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... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ UART1 ADC1 PWM1-2 QEI CNx I2C1 Preliminary PORTA PORTB 16 Remappable Pins PWM 2 Ch PWM 6 Ch © 2007 Microchip Technology Inc. ...
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... O CMOS Position Up/Down Counter Direction State. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Analog = Analog input ...
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... Analog Analog voltage reference (high) input. REF Analog Analog voltage reference (low) input. REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels DS70265B-page 10 Description Analog = Analog input O = Output Preliminary © 2007 Microchip Technology Inc. P=Power I = Input ...
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... operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the dsPIC33FJ12MC201/ 202 is shown in Figure 2-2. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 2.1 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory ...
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... PCH PCL X RAM Y RAM Address Address Loop Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2007 Microchip Technology Inc. ...
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... Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM ...
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... IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70265B-page 14 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (2) Preliminary DS70265B-page 15 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70265B-page 16 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
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... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit will always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 17 ...
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... A block diagram of the DSP engine is shown in Figure 2-3. Algebraic Operation – y – y change – – Preliminary ACC Write Back Yes No No Yes No Yes Yes © 2007 Microchip Technology Inc. ...
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... FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill DS70265B-page 19 ...
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... Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section 6.0 “Interrupt Controller”). This allows the user application to take immediate action, for example, to correct system gain. Preliminary previously and the SAT<A:B> trap when set and the © 2007 Microchip Technology Inc. ...
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... MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: • ...
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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. Preliminary © 2007 Microchip Technology Inc. ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 3-1: PROGRAM MEMORY MAP FOR dsPIC33FJ12MC201/202 DEVICES © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 3.1 Program Address Space The program dsPIC33FJ12MC201/202 devices is 4M instructions ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2007 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70265B-page 26 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0x0BFE 0x0C00 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2007 Microchip Technology Inc. ...
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... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 27 ...
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TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12MC202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — ...
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TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 3-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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... TABLE 3-8: 6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ12MC202 SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA — — — — ...
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TABLE 3-10: 2-OUTPUT PWM2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P2TCON 05C0 PTEN — PTSIDL — P2TMR 05C2 PTDIR P2TPER 05C4 — P2SECMP 05C6 SEVTDIR PWM2CON1 05C8 — — — — PWM2CON2 05CA ...
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TABLE 3-13: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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... TABLE 3-15: ADC1 REGISTER MAP FOR dsPIC33FJ12MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD 031A ...
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TABLE 3-16: ADC1 REGISTER MAP FOR dsPIC33FJ12MC201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... RPINR21 06AA — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12MC202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
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... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-21: PORTB REGISTER MAP FOR dsPIC33FJ12MC202 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C8 TRISB15 TRISB14 TRISB13 ...
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TABLE 3-23: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> PLLFBD 0746 — — — — OSCTUN 0748 — ...
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... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary © 2007 Microchip Technology Inc. addressing modes are ...
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... Not all instructions support all the address- ing modes given above. Individual instruc- tions may support different subsets of these addressing modes. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
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... MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary the difference between the © 2007 Microchip Technology Inc. ...
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... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 3.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION ...
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... Preliminary A0 Decimal © 2007 Microchip Technology Inc. ...
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... User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 3.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70265B-page 46 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2007 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... PSV Area 0x800000 Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2007 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions ...
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... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the operation is (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. required for Preliminary finished. Setting the WR bit © 2007 Microchip Technology Inc. ...
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... No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) U-0 U-0 — — (1) U-0 ...
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... Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70265B-page 52 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2007 Microchip Technology Inc. ...
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... DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Any active source of Reset makes the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
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... If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70265B-page 56 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1> POR (RCON<0>) Note: All Reset flag bits can be set or cleared by the user software. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) (CONTINUED) Setting Event Trap conflict event Illegal opcode or uninitialized W register access Configuration mismatch ...
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... Preliminary FSCM Notes Delay — FSCM FSCM LOCK FSCM — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — 3 © 2007 Microchip Technology Inc. ...
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... SYSRST is released valid clock source is not available at this time, the device automatically switches to the FRC oscillator and the user application can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources ...
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... NOTES: DS70265B-page 60 Preliminary © 2007 Microchip Technology Inc. ...
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... These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1 ...
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... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70265B-page 62 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC33FJ12MC201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2007 Microchip Technology Inc. ...
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... IEC0–IEC4 The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 6.3.4 IPC0–IPC18 The IPC registers are used to set the interrupt priority level for each source of interrupt ...
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... U = Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/W-0 R/W-0 US EDT R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
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... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 COVAERR COVBERR ...
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... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70265B-page 68 Preliminary © 2007 Microchip Technology Inc. ...
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... Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — U-0 ...
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... OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70265B-page 70 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 71 ...
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... SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70265B-page 72 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... QEIIF: QEI Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — QEIIF U-0 ...
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... Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS70265B-page 74 U-0 U-0 R/W-0 — — FLTA2IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 U-0 PWM2IF — bit 8 U-0 U-0 U1EIF — bit Bit is unknown ...
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... Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70265B-page 76 Preliminary © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request enabled 0 = Interrupt request not enabled bit 8-0 Unimplemented: Read as ‘0’ DS70265B-page 78 U-0 U-0 R/W-0 — — QEIIE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 U-0 PWM1IE — bit 8 U-0 U-0 — — bit Bit is unknown ...
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... PWM2IE: PWM2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — FLA2IE U-0 U-0 U-0 — ...
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... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70265B-page 80 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 83
... Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-1 — — ...
Page 84
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70265B-page 82 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 85
... Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — — R/W-0 U-0 R/W-1 — ...
Page 86
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70265B-page 84 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 87
... Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ...
Page 88
... Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70265B-page 86 U-0 U-0 U-1 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 89
... Unimplemented: Read as ‘0’ bit 6-4 PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — ...
Page 90
... Bit is cleared U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 91
... Interrupt source is disabled bit 6-4 PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — R/W-0 U-0 U-0 — — ...
Page 92
... Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70265B-page 90 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 93
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 94
... NOTES: DS70265B-page 92 Preliminary © 2007 Microchip Technology Inc. ...
Page 95
... Oscillator Secondary Oscillator SOSCO LPOSCEN SOSCI Note 1: See Figure 7-2 for PLL details. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 • An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used ...
Page 96
... PLL output ‘F EQUATION 7-2: FNOSC<2:0> POSCMD<1:0> Preliminary is divided OSC ). MHz are supported by the , is given by: DEVICE OPERATING FREQUENCY OSC ‘N1’ is selected using the IN ’ is given by: OSC F CALCULATION OSC ( ) OSC IN N1*N2 © 2007 Microchip Technology Inc. ’, ...
Page 97
... Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 EQUATION 7-3: F OSC ...
Page 98
... FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ DS70265B-page 96 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 99
... OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 97 ...
Page 100
... Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70265B-page 98 R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 101
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 102
... Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) DS70265B-page 100 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 103
... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits ...
Page 104
... NOTES: DS70265B-page 102 Preliminary © 2007 Microchip Technology Inc. ...
Page 105
... EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 8.2 Instruction-Based Power-Saving Modes dsPIC33FJ12MC201/202 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 106
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible ® DSC © 2007 Microchip Technology Inc. ...
Page 107
... CK WR Port Data Latch Read LAT Read Port © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled ...
Page 108
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary © 2007 Microchip Technology Inc. ...
Page 109
... I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used ...
Page 110
... QEB RPINR14 INDX RPINR15 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1 RPINR20 SS1 RPINR21 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> FLTA1R<4:0> FLTA2R<4:0> QEAR<4:0> QEBR<4:0> INDXR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> © 2007 Microchip Technology Inc. ...
Page 111
... SDO1 SCK1OUT SS1OUT OC1 OC2 UPDN © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin (see Table 9-2 and Figure 9-3). The list of peripherals for output mapping also includes a null value of 00000 technique ...
Page 112
... The unlock sequence must be executed as an assembly-language routine, in the same manner as changes to the oscillator configuration, because the unlock sequence is timing-critical. If the bulk of the application is written another high-level language, the unlock sequence should be performed by writing inline assembler. Preliminary © 2007 Microchip Technology Inc. ...
Page 113
... Configuration Example Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 EXAMPLE 9-2: //************************************* // Unlock Registers //************************************* asm volatile ( " ...
Page 114
... Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ DS70265B-page 112 of devices R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 115
... Unimplemented: Read as ‘0’ bit 4-0 INTR2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R<4:0> ...
Page 116
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70265B-page 114 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 117
... Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 118
... IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70265B-page 116 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 119
... Unimplemented: Read as ‘0’ bit 4-0 FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> ...
Page 120
... Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70265B-page 118 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 FLTA2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... Unimplemented: Read as ‘0’ bit 4-0 QEA1R<4:0>: Assign A(QEA) to the corresponding pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 R/W-1 QEA1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 122
... Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70265B-page 120 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INDX1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 123
... Unimplemented: Read as ‘0’ bit 4-0 U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ...
Page 124
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70265B-page 122 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 125
... Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin 11111 = Input tied V SS 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 SS1R< ...
Page 126
... DS70265B-page 124 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP3R<4:0> R/W-0 R/W-0 R/W-0 RP2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 127
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 ...
Page 128
... DS70265B-page 126 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP11R<4:0> R/W-0 R/W-0 R/W-0 RP10R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 129
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 ...
Page 130
... NOTES: DS70265B-page 128 Preliminary © 2007 Microchip Technology Inc. ...
Page 131
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the TCKPS< ...
Page 132
... External clock from pin T1CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ DS70265B-page 130 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 133
... Only T2CON control bits are used for setup and control. Timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 11.1 32-bit Operation To configure the Timer2/3 feature timers for 32-bit operation: 1 ...
Page 134
... T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70265B-page 132 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2007 Microchip Technology Inc. ...
Page 135
... FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70265B-page 133 ...
Page 136
... In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. DS70265B-page 134 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 137
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 (1) — — R/W-0 ...
Page 138
... NOTES: DS70265B-page 136 Preliminary © 2007 Microchip Technology Inc. ...
Page 139
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 3. Prescaler Capture Event modes: - Capture timer value on every 4th rising edge of input at ICx pin ...
Page 140
... DS70265B-page 138 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 141
... Section 6.0 “Interrupt Controller” initiate another single pulse output, change the Timer and Compare register settings, if needed, © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 and then issue a write to set the OCM bits to ‘100’. Disabling and re-enabling the timer, and clearing ...
Page 142
... MIPS log 10 F PWM log (2) 10 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 10 Preliminary CALCULATING THE PWM PERIOD • (Timer Prescale Value) CY show example PWM ) bits = 16 MHz and a Timer2 CY © 2007 Microchip Technology Inc. ...
Page 143
... Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 8. 2: OCFA pin controls OC1-OC2 channels. 3: TMR2/TMR3 can be selected via OCTSEL (OCxCON<3>) bit. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 61 Hz 122 Hz 977 Hz ...
Page 144
... Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled DS70265B-page 142 U-0 U-0 U-0 — — — R-0 HC R/W-0 R/W-0 OCFLT OCTSEL HS = Set in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 OCM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 145
... Fault pins to optionally drive each of the PWM output pins to a defined state • Duty cycle updates configurable to be immediate or synchronized to the PWM time base © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 14.1 PWM1: 6-Channel PWM Module This module simplifies the task of generating multiple synchronized PWM outputs ...
Page 146
... Override Logic PWM Generator Channel 2 Dead-Time #2 Generator and Override Logic PWM Generator Channel 1 Dead-Time #1 Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR Preliminary PWM1H3 PWM1L3 PWM1H2 Output PWM1L2 Driver Block PWM1H1 PWM1L1 FLTA1 Special Event Trigger © 2007 Microchip Technology Inc. ...
Page 147
... Fault Pin Control SFRs P2FLTACON PWM Manual P2OVDCON Control SFR P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 PWM Generator # 1 P2DC1Buffer P2DC1 Comparator Channel 1 Dead-Time Generator and Override Logic Special Event Postscaler SEVTDIR PTDIR ...
Page 148
... The postscaler selection bits can be used in this mode of the timer to reduce the frequency of interrupt events. TCON SFR. X Preliminary TMR register is X TPER register occurs X TPER reg- X TPER register occurs. The X TPER X TMR SFR is read-only and X © 2007 Microchip Technology Inc. ...
Page 149
... X • A write to the P TCON register X • Any device Reset The P TMR register is not cleared when P X written. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 14.4 PWM Period P TPER is a 15-bit register used to set the counting X TMR register X period for the PWM time base. P buffered register ...
Page 150
... PxTMR register matches the value in the PxTPER register. The contents of the duty cycle buffers are automatically loaded into the Duty PTMR Cycle registers when the PWM time base is disabled Value (PTEN = 0). Preliminary © 2007 Microchip Technology Inc. ...
Page 151
... PWM outputs as follows: • PxDC1 register controls PWM1H/PWM1L outputs • PxDC2 register controls PWM2H/PWM2L outputs • PxDC3 register controls PWM3H/PWM3L outputs © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Complementary mode is selected for each PWM pin pair by clearing the appropriate PMODx bit in the PWMxCON1 SFR ...
Page 152
... On a write to the PxDTCON1 or PxDTCON2 registers. • On any device Reset. Note: The user application should not modify the PxDTCON1 or PxDTCON2 values while the PWM module is operating (PTEN = 1). Unexpected results can occur. Preliminary © 2007 Microchip Technology Inc ...
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... PxOVDCON register, the output signal is forced to be the complement of the corresponding PWMxH pin in the pair. Dead-time insertion is still performed when PWM channels are overridden manually. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 14.12.2 OVERRIDE SYNCHRONIZATION If the OSYNC bit in the PWMxCON2 register is set, all output overrides performed via the PxOVDCON register are synchronized to the PWM time base ...
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... UDIS = 1. If the IUE bit is set, any change to the Duty Cycle registers will be immediately updated regardless of the UDIS bit state. The PWM Period register (PxTPER) updates are not affected by the IUE control bit. Preliminary © 2007 Microchip Technology Inc. ...
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... If the SEVTDIR bit is set, the Special Event Trig- ger occurs on the downward count cycle of the PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Count mode. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 14.16.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio ...
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... PWM time base operates in Single Pulse mode 00 = PWM time base operates in a Free-Running mode DS70265B-page 154 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 PTCKPS<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1:64 prescale) CY (1:16 prescale) CY (1:4 prescale) CY (1:1 prescale) CY Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 PTMOD<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... SEVTDIR is compared with PTDIR (P 2: PxSECMP<14:0> is compared with P DS70265B-page 156 R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 R/W-0 R/W-0 (2) SEVTCMP<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) TMR<15>) to generate the Special Event Trigger. X TMR<14:0> to generate the Special Event Trigger. X Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only 1 PWM I/O pin pair. PWM1 on dsPIC33FJ12MC201 devices supports only two PWM I/O pin pairs. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (2) U-0 U-0 R/W-0 — ...
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... Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled DS70265B-page 158 U-0 R/W-0 R/W-0 — SEVOPS<3:0> U-0 U-0 R/W-0 — — IUE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared boundary CY Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 OSYNC UDIS bit Bit is unknown ...
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... Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 DTB<5:0> ...
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... Dead time provided from Unit A Note 1: PWM2 supports only 1 PWM I/O pin pair. DS70265B-page 160 (1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DTS3I DTS2A DTS2I U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 DTS1A DTS1I bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only 1 PWM I/O pin pair. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 (1) R/W-0 R/W-0 R/W-0 FAOV3L ...
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... PWMx I/O pin is driven inactive when the corresponding POVDxH:POVDxL bit is cleared Note 1: PWM2 supports only 1 PWM I/O pin pair. DS70265B-page 162 (1) R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... REGISTER 14-12: P1DC2: PWM DUTY CYCLE REGISTER 2 R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC2<15:0>: PWM Duty Cycle #2 Value bits © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PDC2<15:8> ...
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... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle #3 Value bits DS70265B-page 164 R/W-0 R/W-0 R/W-0 PDC3<15:8> R/W-0 R/W-0 R/W-0 PDC3<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... PCDOUT Existing Pin Logic 0 UPDN Up/Down 1 © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode • ...
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... Position counter reset by detection of index pulse, QEIM<2:0> = 110. • Position counter reset by match with MAXCNT, QEIM<2:0> = 111. The x4 Measurement mode provides for finer resolution data (more position counts) for determining motor position. Preliminary © 2007 Microchip Technology Inc. ...
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... Changing the operational mode (for exam- ple, from QEI to timer or vice versa) will not affect the Timer/Position Count register contents. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 The UPDN control/status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer counts up. When UPDN = 0, the timer counts down. In addition, control bit UPDN_SRC, (in QEICON< ...
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... Note: The POSCNT accesses,. However, reading the register in Byte mode can result in partially updated values in subsequent reads. Either use Word mode reads/writes, or ensure that the counter is not counting during Byte operations. Preliminary © 2007 Microchip Technology Inc. register allows byte ...
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... Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin Position Counter Direction Status Output Disabled (Normal I/O pin operation) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R-0 R/W-0 R/W-0 INDEX ...
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... UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction Note: When configured for QEI mode, control bit is a ‘don’t care’. DS70265B-page 170 Preliminary © 2007 Microchip Technology Inc. ...
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... Clock Divide 110 = 1:128 Clock Divide 101 = 1:64 Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/W-0 — — IMV<2:0> U-0 U-0 — ...
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... NOTES: DS70265B-page 172 Preliminary © 2007 Microchip Technology Inc. ...
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... The module will not respond to SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPIxBUF is read by user software. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 16.3 Transmit Operations Transmit writes are also double-buffered. The user application writes to SPIxBUF ...
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... SPI error conditions. 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary registers with MSTEN 1:1/4/16/64 F Primary CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...
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... User application must write transmit data to or read received data from SPIxBUF. The SPIxTXB and SPIxRXB regis- ters are memory mapped to SPIxBUF. FIGURE 16-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F FIGURE 16-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx ...
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... Invalid 10000 4:1 10000 5000 16:1 2500 1250 64:1 625 312.5 156.25 1:1 5000 2500 4:1 1250 625 16:1 313 156 64 Preliminary 4:1 6:1 8:1 6666.67 5000 2500 1666.67 1250 625 416.67 312.50 104.17 78.125 1250 833 625 313 208 156 © 2007 Microchip Technology Inc. ...
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... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
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... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70265B-page 178 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 Preliminary DS70265B-page 179 ...
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... Unimplemented: This bit must not be set to ‘1’ by the user application. DS70265B-page 180 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 FRMDLY — bit Bit is unknown ...
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... C master operation with 7- or 10-bit address For details about the communication sequence in each of these modes, refer to the “dsPIC33F Family Reference Manual” . Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F Family Reference Manual chapters. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 2 17 Registers I2CxCON and I2CxSTAT are control and status registers, respectively ...
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... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...
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... The control bit IPMIEN enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 17.8 General Call Address Support The general call address can address all devices. ...
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... C module has limited peripheral pin select functionality. When the ALTI2C bit in the FPOR configuration register is set to ‘1’, I SDAx/SLCx pins. When ALTI2C bit is ‘0’, I uses ASDAx/ASCLx pins.\ Preliminary © 2007 Microchip Technology Inc port to its Idle state module uses 2 ...
Page 187
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 188
... Start condition not in progress DS70265B-page 186 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master) Preliminary 2 C master) © 2007 Microchip Technology Inc. ...
Page 189
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 R/C-0 HS — ...
Page 190
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70265B-page 188 2 C slave device address byte. Preliminary © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 U-0 U-0 U-0 — ...
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... NOTES: DS70265B-page 190 Preliminary © 2007 Microchip Technology Inc. ...
Page 193
... FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 • Hardware flow control option with UxCTS and UxRTS pins • Fully integrated Baud Rate Generator with 16-bit prescaler • Baud rates ranging from 1 Mbps to 15 Mbps at 16 MIPS • ...
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... Desired Baud Rate Preliminary UART BAUD RATE WITH BRGH = Baud Rate = 4 • (BRGx + BRGx = – • Baud Rate denotes the instruction cycle clock /2). OSC CY © 2007 Microchip Technology Inc. /4 ...
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... Write 0x55 to UxTXREG, which loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 18.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 18.2 “ ...
Page 196
... This feature is only available for the 16x BRG mode (BRGH = 0). DS70265B-page 194 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 MODE REGISTER (CONTINUED) x Preliminary DS70265B-page 195 ...
Page 198
... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). DS70265B-page 196 STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. dsPIC33FJ12MC201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary ...
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... NOTES: DS70265B-page 198 Preliminary © 2007 Microchip Technology Inc. ...