STSMIA832 STMicroelectronics, STSMIA832 Datasheet
STSMIA832
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STSMIA832 Summary of contents
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... Mobile Phone and Portable Battery Equipment. A configurable input (Class_Sel) is provided to select different CLASS (0 or 1,2) mode inside the SMIA STD specifications. The STSMIA832 is offered in a µTFBGA package to optimize PCB space. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity from transient excess voltage ...
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... Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Power saving at the inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Switching off digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 Disabling the outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6 Load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.8 Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Frame structure Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/ STSMIA832 ...
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... STSMIA832 1 Schematic diagram Figure 1. Simplified application block diagram Figure 2. Block diagram Schematic diagram 3/23 ...
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... Differential strobe receiver inputs (Class_Sel = VL) Differential clock receiver inputs (Class_Sel = GND) Receivers enable input Clock output Horizontal sync output Vertical sync output Ground (Digital I/O reference) Ground (Analog subLVDS part) Core supply voltage Digital I/O supply voltage Select sync input Select CLASS input STSMIA832 ...
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... CLASS_SEL pin selection mode, Data/Clock signaling or Data/Strobe signaling modes are activated. D1-D8, CLK STSMIA832 output data and clock lines. Parallel 8 bits of CMOS/LVTTL data is output at a maximum data rate of 82Mbps per line. Output LVTTL clock is transmitted in parallel with the data at 82MHz Max. SYNC-SEL ...
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... CCP2 is based on signaling scheme called SubLVDS, which is current mode differential low voltage signaling method modified from the IEEE 1596.3 LVDS standard for reduced power consumption. STSMIA832 operates in a data/strobe signaling mode. The use of data-strobe coding together with SubLVDS enables the use of high data rates with low EMI ...
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... STSMIA832 . Figure 5. Data-Strobe signaling Data is sent byte-wise LSB first. The state of the data and strobe signals at the beginning of transmission are fixed i.e. the state of data is logic high and the state of strobe is logic low. The number of clock cycles between synchronization codes has to be even, both between SOL (or SOF) – ...
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... X = channel number 8/23 Synchronization Codes FFH 00H 00H X0H FFH 00H 00H X1H FFH 00H 00H X2H FFH 00H 00H X3H STSMIA832 Notes Line Start Code Line End Code Frame Start Code Frame End Code DMA Channel Identifier from Channel ...
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... EN pin. The maximum quiescent supply current gets reduced to I initiated by applying a low-level pulse to the EN input of STSMIA832 device. The device remains state, drawing minimal power, until EN goes High, at which point it returns to full operation. ...
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... A reduced external capacitance leads to reduced current consumption and also reduced rise time and fall time. The parallel output driving capacitance in STSMIA832 is 10pF and the rise time and fall times for the LVTTL parallel outputs are 2.2ns maximum. ...
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... STSMIA832 . Figure 9. STSMIA832 Load capacitance and rise and fall time of LVTTL parallel outputs 3.7 Board layout To obtain the maximum benefit from the noise and EMI reductions of subLVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals ...
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... CLK SMIA disabled H Start of Frame L End of Frame See Detailed H Timing Diagram L D+, D- See Disabled Sync data in Detailed (D1-D8 will get L parallel Timing out data, including mode Diagram CLASS_SEL Data/Clock GND Data/Strobe Data/Strobe STSMIA832 FUNCTION Start of Line End of Line Sync Code ...
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... STSMIA832 4 Maximum ratings Table 5. Absolute maximum ratings Symbol V Main Supply Voltage DD V Secondary Supply Voltage L V SubLVDS Data Bus Input Voltage (D+, D SubLVDS Clock Bus Input Voltage (STRB+, STRB-) STRB V DC Input Voltage (SYNC_SEL, CLASS_SEL, EN Output Voltage (D1-D8, H-SYNC, V-SYNC, CLK) ...
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... 2.65V to 3. 1.65V to 1.95V 0.7xV 0.3xV -4mA +4mA OL Test Conditions V ( 1.65V to 1.95V, L 2. GND STSMIA832 Min. Typ. Max. 0.5 0.9 1.3 -25 +25 ±10 ±10 3.5 9.0 DD, 10 0.7xV 3. 0.3xV L ±10 ±10 1.25 0.30 Value T = 25°C A Min. Typ. Max. ...
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... STSMIA832 Table 9. Switching characteristics (R = 100 ± 1 noted. Typical values are referred to T Symbol Parameter Rise Time LVTTL Output Voltage t r (10% to 90%) Fall Time LVTTL Output Voltage t f (90% to 10%) Propagation Delay Time (STRB to t pLH V-SYNC, H-SYNC) Low to High Propagation Delay Time (STRB to ...
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... Frame structure. 6 Frame structure Figure 11. Frame structure in VGA case (allowed synchronization codes sequence) Figure 12. Bit order in synchronization codes and data, LSB first (example start of frame), image frame structure 1. LSB (bytewise Least Significant Bit first) 16/23 . STSMIA832 ...
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... STSMIA832 7 Timing diagram (unless otherwise specified T Figure 13. Disabled Sync Mode (SYNC_SEL = GND) (D1-D8 will transmit the input data DIN, including SYNC CODE) and CLASS_SEL = V 1. Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal extracted clock having half frequency respect to the external clock. All others are output signals. ...
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... Figure 14. Enabled sync mode (SYNC_SEL = VDD) (D1-D8 will transmit the input data DIN, excluding SYNC CODE) and CLASS_SEL = V 1. Note: DATA_IN and STROBE are the input signals, CLKH is an internal signal i.e internal extracted clock having half frequency respect to the external clock. All others are output signals. 18/23 L STSMIA832 ...
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... STSMIA832 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... Package mechanical data DIM. MIN 0.78 b 0. 20/23 TFBGA25 MECHANICAL DATA mm. TYP MAX. 1.1 1.16 0.25 0.86 0.30 0.35 3.0 3.1 2 3.0 3.1 2 0.5 0.25 STSMIA832 mils MIN. TYP. MAX. 39.4 43.3 30.7 9.8 11.8 114.2 118.1 122.0 78.8 114.2 118.1 122.0 78.8 19.7 9.8 7539979/A 45.7 9.8 33.9 13.8 ...
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... STSMIA832 Tape & Reel TFBGA25 MECHANICAL DATA DIM. MIN 12 3.9 P 7.9 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 14.4 3.3 3.3 1.60 4.1 0.153 8.1 0.311 Package mechanical data inch TYP. MAX. 12.992 0.519 0.567 0.130 0.130 0.063 0.161 0.319 21/23 ...
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... Revision history 9 Revision history Table 10. Revision history Date Revision 13-Mar-2006 1 3-May-2006 2 22/23 Initial release. Mistake on table 3 - Output. STSMIA832 Changes ...
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... STSMIA832 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...