HMP8156 Intersil Corporation, HMP8156 Datasheet
HMP8156
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HMP8156 Summary of contents
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... Copyright Description The HMP8156 NTSC and PAL encoder is designed for use in systems requiring the generation of high-quality NTSC and PAL video from digital image data. YCbCr or RGB digital video data drive the P0-P23 inputs. Overlay inputs are processed and the data is 2x upsampled. ...
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... HMP8156 2 ...
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... The RGB data may be linear or gamma corrected; if enabled, the encoder will gamma correct the input data. Overlay Data The HMP8156 accepts 5 bits of pixel overlay input data and combines it with the input pixel data. The data specifies an overlay color and the fractions of the new and original colors to be summed ...
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... Cb and Cr data. The upsampling func- tion uses linear interpolation. OVERLAY PROCESSING The HMP8156 accepts overlay data via the OL0-OL2, M0, and M1 pins. Overlay mixing is done using the 4:4:4 YCbCr pixel data from the color space converter. The YCbCr data following overlay processing is used as input data by the video processing functions ...
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... Upscaling Following overlay processing, 2X upscaling may optionally be applied to the pixel data. In this mode, the HMP8156 accepts SIF resolution video 59.94 frames per sec- ond and generates standard interlaced video at 262.5 lines per field (240 active) at 59.94 fields per second for (M, NSM) NTSC and (M) PAL, and 312.5 lines per fi ...
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... P8-P15 Cb 0 OL0-OL2, PIXEL 0 M1, M0 BLANK (INPUT) BLANK (OUTPUT) FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITHOUT 2X UPSCALING HMP8156 VIDEO TIMING CONTROL (NOTE) OVERLAY DATA INPUT SAMPLE Same edge that Every rising edge Any rising edge of latches Y of CLK2 CLK2 ...
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... Cb 0 OL0-OL2, PIXEL 0 M1, M0 BLANK (INPUT) BLANK (OUTPUT) FIGURE 3. PIXEL AND OVERLAY INPUT TIMING 6-BIT YCBCR WITHOUT 2X UPSCALING HMP8156 PIXEL 1 PIXEL 2 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with 2X Upscaling When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected and 2X upscaling is enabled, data is latched on the rising edge of CLK2 while CLK is low ...
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... FIGURE 5. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITHOUT 2X UPSCALING CLK2 CLK P8-P15 P0-P7 OL0-OL2, M1, M0 BLANK (INPUT) BLANK (OUTPUT) FIGURE 6. PIXEL AND OVERLAY INPUT TIMING - 16-BIT YCBCR WITH 2X UPSAMPLING HMP8156 RGB 1 RGB 2 RGB 3 RGB 4 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 RGB 1 RGB 2 RGB 3 ...
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... Y data. The pixel and overlay input timing is shown in Figure 9. As inputs, the BLANK, HSYNC, and VSYNC pins are ignored since all timing is derived from the EAV and SAV sequences within the data stream. As outputs, BLANK, HMP8156 RGB 0 RGB 1 PIXEL 0 PIXEL 1 ...
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... Video Timing Control The pixel and overlay data must be presented to the HMP8156 59.94 fields per second (interlaced). The video timing is controlled by the BLANK, HSYNC, VSYNC, FIELD, and CLK2 pins. HSYNC, VSYNC, and FIELD Timing The leading edge of HSYNC indicates the beginning of a horizontal sync interval ...
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... CLK cycle when the blank tim- ing select bit is cleared. The active video may also appear to end early or start late since the HMP8156 controls the blank- ing edge rates. The delay from the active edge of HSYNC to the 50% point of the composite sync is 4-39 CLK2 cycles depending on the HMP8156 operating mode ...
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... Figure 13. At this point, the HMP8156 also scales the Y data to generate the proper output levels for the vari- ous video standards The HMP8156 lowpass filters the Cb and Cr data to 1.3MHz prior to modulation. The lowpass filtering removes any alias- ing artifacts due to the upsampling process (simplifying the analog output fi ...
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... This allows the generation of “safe” video in the event non- standard YCbCr values are input to the device. Closed Captioning If enabled in the auxiliary data control register, the HMP8156 generates closed captioning data on specified scan lines. PAL SQUARE PIXEL The captioning data stream includes clock run-in and start CLK2 = 29 ...
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... VREF must be chosen such that it is within the part’s operat- ing range; RSET must be chosen such that the maximum output current is not exceeded. If the VREF pin is not connected, the HMP8156 provides an internal reference voltage. Otherwise, the applied voltage overdrives the internal reference external reference is used, it must decoupled from any power supply noise ...
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... HMP8156 Host Interfaces Reset The HMP8156 resets to its default operating mode on power up, when the reset pin is asserted for at least four CLK cycles, or when the software reset bit of the host control reg- ister is set. During the reset cycle, the encoder returns its internal registers to their reset state and deactivates the I interface ...
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... C interface. All internal registers may be written or read by the host processor at any time. However, some of the bits and words are read only or reserved and data written to these bits is ignored. Table 9 lists the HMP8156’s internal registers. Their bit descriptions are listed in Tables 10-27. BIT NUMBER ...
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... Lower limit of composite active video is about half the sync height 5 SCH Phase 0 = Never reset SCH phase Mode 1 = Reset SCH phase every 4 (NTSC (PAL) fields 4-0 Reserved HMP8156 TABLE 12. INPUT FORMAT REGISTER SUB ADDRESS = 02 H DESCRIPTION TABLE 13. VIDEO PROCESSING REGISTER SUB ADDRESS = 03 H ...
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... Closed caption enabled for even fields: line 284 for NTSC, line 281 for (M) PAL, or line 335 for ( CN) PAL 11 = Closed caption enabled for both odd and even fields 5-0 Reserved HMP8156 TABLE 14. TIMING I/O REGISTER #1 SUB ADDRESS = 04 H DESCRIPTION TABLE 15. TIMING I/O REGISTER #2 ...
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... This register is cascaded with the closed caption_284B data register and they are read Data out serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit (First Byte the 284A data register is shifted out first. HMP8156 TABLE 17. HOST CONTROL REGISTER SUB ADDRESS = 0F H DESCRIPTION ...
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... This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start Output Signal inputting pixel data each scan line. The leading edge of HSYNC is count 000 (Horizontal) ister is ignored unless BLANK is configured as an output. HMP8156 SUB ADDRESS = 13 H DESCRIPTION TABLE 22. START H_BLANK LOW REGISTER ...
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... The leading edge of VSYNC at the start of an odd field is count 000 not follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is configured as an output. HMP8156 TABLE 25. START V_BLANK LOW REGISTER SUB ADDRESS = 23 H DESCRIPTION TABLE 26 ...
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... P0-P15 58, 55-43, 38, 37 P16-P23 32-27, 23, 22 FIELD 34 O HSYNC 35 I/O VSYNC 36 I/O BLANK 33 I/O CLK 39 I/O HMP8156 HMP8156 (PQFP) TOP VIEW Pixel input pins. See Table 1. ...
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... VREF 61 I FS_ADJUST 62 COMP 1 64 COMP 2 63 VAA GND HMP8156 DESCRIPTION 2x pixel clock input. This clock must be a continuous, free-running clock interface clock input interface address select input interface data input/output. The circuit for this pin should include a 4-6k pull up resistor connected to VAA ...
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... Output Logic High Voltage Output Capacitance, C OUT DC PARAMETERS, ANALOG OUTPUTS DAC Resolution Integral Nonlinearity, INL Differential Nonlinearity, DNL HMP8156 Thermal Information Thermal Resistance (Typical, Note 1) PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range . . . . . . . . . o C Maximum Lead Temperature (Soldering 10s 300 ...
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... Control Hold Time CLK Frequency CLK High Time, CLK H CLK Low Time, CLK L CLK2 Frequency HMP8156 = +5V 5%, RSET = 124 , VREF_IN = 1.225V, Unless otherwise specified (Continued) TEST CONDITION I = 0mA, CLK = 13.5MHz OUT Note 2 Pin not driven, using internal reference Pin not driven, using internal reference ...
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... NOISE LEVEL = -79.9dB RMS -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 -70.0 -75.0 -80.0 -85.0 -90.0 -95.0 -100.0 1.0 2.0 3.0 AVERAGE (MHz) FIGURE 17. NOISE SPECTRUM (NTSC) HMP8156 = +5V 5%, RSET = 124 , VREF_IN = 1.225V, Unless otherwise specified (Continued) TEST CONDITION 2 C Bus Interface specification. Note 4 Note 3 APL = 44.3% 4.0 5.0 SETUP 7.5% FIGURE 18. NTSC COLOR BAR VECTOR SCOPE PLOT 26 MIN TYP MAX UNITS 13 ...
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... AVERAGE FIGURE 20. LUMINANCE NON LINEARITY (NTSC) HMP8156 (Continued) FIGURE 19. NTSC FCC COLOR BAR wfm ---> 5 STEP PK-PK = 2.1 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.734 (kHz) FIELD FREQUENCY 59.94 (Hz) 4TH 5TH AVERAGE OFF FIGURE 21. LINE FREQUENCY (NTSC) 27 0.00 (%) -0.2 0.0 0.2 0.4 ...
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... Typical Performance Curves LINE JITTER (LINE 20 TO 250) FIGURE 22. H SYNC JITTER IN A FRAME (NTSC) AVERAGE FIGURE 24. NOISE SPECTRUM (PAL) HMP8156 (Continued) 525 LINE NTSC 2ns P-P MEAN SCH 0.8 DEGREES AVERAGE FIGURE 23. SCH PHASE MEASUREMENT APL = 40.0% FIGURE 25. PAL COLOR BAR VECTOR SCAPE PLOT ...
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... AVERAGE FIGURE 27. LUMINANCE NON LINEARITY (PAL) HMP8156 (Continued) FIGURE 26. COLOURBAR (PAL) wfm ---> 5 STEP PK-PK = 1.4 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.625 (kHz) FIELD FREQUENCY 50.00 (Hz) AVERAGE OFF 4TH 5TH FIGURE 28. LINE FREQUENCY (PAL) 29 Wfm ---> COLOUR BAR 0.00 (%) -0.2 0.0 ...
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... All GND pins on the HMP8156 must be connected to the ground plane. Typical power and ground planes are shown in Figure 31. The HMP8156 should have its own power plane that is iso- lated from the common power plane of the board, with a gap between the two power planes of at least 1/8 inch. All V pins of the HMP8156 must be connected to this HMP8156 power plane ...
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... VCC GND FIGURE 31. EXAMPLE POWER AND GROUND PLANES HMP8156 If a separate linear regulator is used to provide power to the HMP8156 power plane, the power-up sequence should be pins to designed to ensure latchup will not occur. A separate linear reg- AA ulator is recommended if the power supply noise on the V pins exceeds 200mV ...
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... FIGURE 33B. LOW COST FILTER FIGURE 33. EXAMPLE POST-FILTER CIRCUITS available. The The HMP8156EVAL2 is a standard size PC add in card with an ISA bus interface and application software. The HMP8156EVAL2 kit is a complete system which allows dem- onstrating all of the encoder’s operating modes. It has ana- log video inputs for composite, S-video, and component RGB signals ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HMP8156 Q64.14x14 64 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE ...