HMP451S6MMP8C Hynix Semiconductor, HMP451S6MMP8C Datasheet
HMP451S6MMP8C
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HMP451S6MMP8C Summary of contents
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... Fully differential clock operations (CK & CK) ORDERING INFORMATION Part Name HMP451S6MMP8C- Y5/S6 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / May. 2008 • ...
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SPEED GRADE & KEY PARAMETERS Y5 (DDR2-667) Speed@CL3 400 Speed@CL4 533 Speed@CL5 667 Speed@CL6 - CL-tRCD-tRP 5-5-5 ADDRESS TABLE Density Organization Ranks 4GB 512M Rev. 0.1 / May. 2008 1200pin Unbuffered DDR2 SDRAM SO-DIMMs S6 Unit (DDR2-800) ...
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PIN DESCRIPTION Symbol Type Polarity Cross CK[1:0], CK[1:0] Input Point Active CKE[1:0] Input High Active S[1:0] Input Low Active RAS, CAS, WE Input Low BA[2:0] Input Active ODT[1:0] Input High A[9:0], A10/AP, Input A[15:11] DQ[63:0] In/Out Active DM[7:0] Input High ...
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PIN ASSIGNMENT Pin Front Pin Back Pin NO. Side NO. Side NO. 1 VREF 2 VSS 51 3 VSS 4 DQ4 53 5 DQ0 6 DQ5 55 7 DQ1 8 VSS 57 9 VSS 10 DM0 59 11 DQS0 12 ...
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... FUNCTIONAL BLOCK DIAGRAM 4GB(512Mbx64) : HMP451S6MMP8C 3Ω +/-5% CKE1 ODT1 /S1 CKE0 ODT0 /S0 /CS0 ODT0 CKE0 DQS0 DQS /DQS0 /DQS DM0 DM DQ0 I/O 0 DQ1 I/O 1 DQ2 I DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 /CS0 ODT0 CKE0 DQS1 DQS /DQS1 /DQS DM1 DM DQ8 I/O 0 DQ9 I/O 1 DQ10 I DQ11 I/O 3 DQ12 ...
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ABSOLUTE MAXIMUM RATINGS Parameter Voltage on V pin relative to Vss DD Voltage on V pin relative to Vss DDQ Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Operating Conditions and Environmental Parameters Parameter ...
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INPUT DC LOGIC LEVEL Parameter dc Input logic HIGH dc Input logic LOW INPUT AC LOGIC LEVEL Parameter Symbol AC Input logic HIGH V (AC Input logic LOW V (AC INPUT TEST CONDITIONS Symbol V Input ...
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Differential Input AC logic Level Symbol Parameter V (ac) ac differential input voltage ID V (ac) ac differential cross point voltage (DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, ...
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OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol V Output Timing Measurement Reference Level OTR Notes: 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol I Output Minimum Source DC Current OH(dc) I Output ...
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... PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°…) 4GB : HMP451S6MMP8C Pin CK, CK CKE, ODT,CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Notes: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Rev. 0.1 / May. 2008 1200pin Unbuffered DDR2 SDRAM SO-DIMMs ...
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... IDD SPECIFICATIONS (T 4GB, 512M x 64 SO-DIMM : HMP451S6MMP8C Y5 Symbol (DDR2 667@CL5) IDD0 2080 IDD1 2400 IDD2P 128 IDD2Q 720 IDD2N 800 IDD3P(F) 560 IDD3P(S) 288 IDD3N 880 IDD4R 3520 IDD4W 3200 IDD5B 4480 IDD6 128 IDD6(L) 80 IDD7 5520 Notes: 1. IDD6 current values are guaranteed up to Tcase of 85c max. ...
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IDD Measurement Conditions Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RAS- IDD0 min(IDD);CKE is HIGH HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs ...
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Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin DDR2-800 Speed (S5) Bin(CL-tRCD-tRP) 5-5-5 Parameter min CAS Latency 5 tRCD 12.5 tRP 12.5 tRAS 45 tRC 57.5 AC Timing Parameters by Speed Grade Parameter Average ...
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Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time (differential strobe) DQ and DM input hold time ...
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Parameter CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a ...
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PACKAGE OUTLINE 512Mx64 - HYMP451S6MMP8 2.00 Min 4.00 +/-0.10 Detail-B PIN 1 PIN 39 PIN 41 2.15 11.40 1.80±0.10 4.20 Detail-B 11.40 2.45 1.50±0.10 PIN 2 PIN 40 PIN 42 Detail of Contacts A 0.45 ±0.03 0.60 Note: 1. All ...
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REVISION HISTORY Revision 0.1 Initial data sheet released Rev. 0.1 / May. 2008 1200pin Unbuffered DDR2 SDRAM SO-DIMMs History Date May. 2008 17 ...