ADRF6601 Analog Devices, Inc., ADRF6601 Datasheet
ADRF6601
Related parts for ADRF6601
ADRF6601 Summary of contents
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... Programmable via 3-wire SPI interface 40-lead × LFCSP APPLICATIONS Cellular base stations GENERAL DESCRIPTION The ADRF6601 is a high dynamic range active mixer with an integrated fractional-N phase-locked loop (PLL) and a voltage- controlled oscillator (VCO) for internal mixer LO generation. Along with the ADRF6602 and the ADRF6603, the ADRF6601 forms a family of integrated PLL/mixers ...
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... Register 6—VCO Control and VCO Enable (Default: 0x1E2106) .................................................................................... 14 Register 7—Mixer Bias Enable and External VCO Enable (Default: 0x000007) .................................................................... 14 Theory of Operation ...................................................................... 15 Programming the ADRF6601 ................................................... 15 Initialization Sequence .............................................................. 15 LO Selection Logic ..................................................................... 16 Applications Information .............................................................. 17 Basic Connections for Operation ............................................. 17 ...
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... Frequency Range Output Level (LO as Output) 1× LO into a 50 Ω load, LO output buffer enabled Input Level (LO as Input) Input Impedance = 38.4 MHz 38.4 MHz; high-side LO injection; f REF PFD Rev Page ADRF6601 = 140 MHz; IIP3 optimized IF Min Typ Max Unit 750 1160 MHz ...
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... ADRF6601 SYNTHESIZER/PLL SPECIFICATIONS VCCx = 5 V; ambient temperature ( 25° 140 MHz; IIP3 optimized using CDAC = 0x1 and IP3SET = 3.3 V, unless otherwise noted. IF Table 3. Parameter Test Conditions/Comments SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO Frequency Range Internally generated LO 1 Figure of Merit f Reference Spurs ...
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... LE pulse width DB2 DB22 (CONTROL BIT C3) (CONTROL BIT C2) Figure 2. Timing Diagram Rev Page 140 MHz; IIP3 optimized IF Min Typ Max 1.4 3.3 0 0.7 0.1 5 4.75 5 5.25 101 179 280 30 DB1 DB0 (LSB) (CONTROL BIT C1 ADRF6601 Unit V V μ ...
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... ADRF6601 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Supply Voltage, VCC1, VCC2, VCC_LO, VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE IFP, IFN RF IN θ (Exposed Paddle Soldered Down) JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device ...
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... THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. Figure 3. Pin Configuration is required. If Bit DB18 is set to 1, the four nominal charge pump currents (I SET × ⎞ 217 ⎟ − Ω ⎟ I ⎠ NOMINAL Rev Page ADRF6601 IN NOMINAL ) can be ...
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... ADRF6601 Pin No. Mnemonic Description 27 VCC_V2I Power Supply. Power supply voltage range is 4. 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. 29 IP3SET Connect a resistor from this pin supply to adjust IIP3. Normally leave open. ...
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... LO FREQUENCY (MHz) Figure 8. IP1dB vs. LO Frequency 0 –40°C +25°C +85°C –10 –20 –30 –40 –50 –60 750 800 850 900 950 1000 1050 LO FREQUENCY (MHz) 50 Ω Termination at RF Port ADRF6601 1100 1150 1100 1150 1100 1150 ...
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... ADRF6601 Phase noise measurements made at IF output, unless otherwise noted. –80 –90 100kHz OFFSET –100 –110 –120 10kHz OFFSET –130 1MHz OFFSET –140 10MHz OFFSET –150 –160 INTERGRATED PHASE NOISE –170 750 800 850 900 950 1000 LO FREQUENCY (MHz) Figure 10. PLL Spot Phase Noise at Various Offsets and Integrated Phase Noise vs. LO Frequency – ...
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... REGISTER STRUCTURE This section provides the register maps for the ADRF6601. The three LSBs determine the register that is programmed. REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 ...
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... ADRF6601 REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B) DITHER DITHER RES MAGNITUDE ENABLE DB23 DB22 ...
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... CPMULT 31 × 22.5°/ CPMULT PFD PHASE OFFSET POLARITY NEGATIVE POSITIVE (DEFAULT) Rev Page ADRF6601 PFD ANTI- CP PFD EDGE BACKLASH CONTROL BITS CONTROL DELAY DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0) ...
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... ADRF6601 REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106) CHARGE 3.3V VCO LDO PUMP ...
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... Analog Devices website (www.analog.com) that allows easy programming from a PC running Windows XP or Vista. INITIALIZATION SEQUENCE To ensure proper power-up of the ADRF6601 important to reset the PLL circuitry after the VCC supply rail settles ± 0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions ...
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... ADRF6601 LO SELECTION LOGIC The downconverting mixer in the ADRF6601 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer ...
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... APPLICATIONS INFORMATION BASIC CONNECTIONS FOR OPERATION Figure 21 shows the basic connections for the ADRF6601. The six power supply pins should be individually decoupled using 100 pF and 0.1 μF capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 21 ...
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... ADRF6601 EVALUATION BOARD Figure 24 shows the schematic of the RoHS-compliant evalua- tion board for the ADRF6601. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material. ...
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... Figure 23. Main Window of the ADRF6601 Evaluation Board Software Rev Page ADRF6601 ...
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... ADRF6601 SCHEMATICS AND ARTWORK 0 R66 C28 10UF 0 VCC_BB R32 0 VCC_LO R31 0 VCC_RF R29 0 R33 0 0 R72 R62 3K R10 0 R37 TC4- R43 R12 DNI R11 Y1 Figure 24. Evaluation Board Schematic Rev Page R34 R20 ...
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... Figure 25. Evaluation Board Layout (Bottom) Figure 26. Evaluation Board Layout (Top) Rev Page ADRF6601 ...
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... RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6601 is ac-coupled; therefore, no bias is necessary output. The differential IF output signals from the ADRF6601 (IFP and IFN) are converted to a single-ended signal by T3. Rev Page Default Condition/ ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page 0.60 MAX PIN 1 INDICATOR 4.25 EXPOSED 4.10 SQ PAD 3.95 (BOT TOM VIEW 0.25 MIN 4.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-40-1 ADRF6601 ...
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... ADRF6601 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08546-0-4/10(0) Rev Page ...