ADRF6702 Analog Devices, Inc., ADRF6702 Datasheet
ADRF6702
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ADRF6702 Summary of contents
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... Baseband Modulation bandwidth: 500 MHz (3 dB) SPI Serial Interface for PLL Programing Power Supply 210 mA 40 Pin 6mm X 6mm LFCSP GENERAL DESCRIPTION The ADRF6702 TxMod modulator with integrated PLL and VCO. The PLL/Synthesizer uses a Fractional-N PLL to generate a 2*F input to the I-Q modulator. The PLL reference LO input is supported from 12MHz to 160MHz ...
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... ADRF6702 SPECIFICATIONS VDD = 5 V; Ambient Temperature ( 25°C; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias; FREF = A 76.8 MHz, Modulator Baseband Frequency = 1 MHz, Output Frequency = 1800 MHz, unless otherwise noted. Table 1. Parameter RF OUTPUT Frequency Range Nominal Output Power Output Harmonics Gain Flatness vs ...
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... Load ≤ (REFIN = 76.8 MHz), Load ≤ (REFIN = 38.4 MHz) Programmable to 250uA, 500uA, 750uA, 1000uA CLK, DATA, LE Pins VDD PLL only Normal Tx Mode Tx Mode with LO Buffer Enabled Power Down Mode Rev. PrE | Page ADRF6702 Min Typ Max Unit -90 dBc/Hz -107 dBc/Hz -127 ...
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... ADRF6702 TIMING CHARACTERISTICS Table 3. Figure2. Timing Diagram Rev. PrE | Page Preliminary Technical Data ...
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... TBD V section of this specification is not implied. Exposure to absolute TBD °C/W maximum rating conditions for extended periods may affect 125°C device reliability. -40°C to +85°C −65°C to +150°C Rev. PrE | Page ADRF6702 ...
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... ADRF6702 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Preliminary Technical Data Figure 3. Block Diagram Rev. PrE | Page ...
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... For further details on the charge pump current, see Register 4 ENOP R5:DB6 LOSEL R5:DB3 (LDRV Rev. PrE | Page through loop filter ) can be externally tweaked NOMINAL ⎤ ⎥ − ⎦ Output 0 DISABLED X DISABLED 1 ENABLED R5:DB5(LDIV) R5:DB4(LXL ADRF6702 ...
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... ADRF6702 THEORY OF OPERATION The ADRF6702 integrates a high performance IQ modulator with a state of the art fractional-N PLL. The PLL also integrates a low noise VCO. The programmable SPI port allows the user to control the fractional-N PLL functions and the modulator optimization functions as well as allowing for an externally applied LO or VCO ...
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... The I and Q inputs are high impedance and should normally be terminated with resistors to provide an appropriate match to the baseband filter which immediately precedes the IQ modulator in the signal chain. Figure 4. Basic Connections for Operation Rev. PrE | Page ADRF6702 ...
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... ADRF6702 DEVICE PROGRAMMING Device programming is effected using a three pin SPI port. The description of timing requirements for the SPI port is given in Figure 2. There are eight programmable registers, each with 24 bits, controlling the operation of the device. The register functions can be broken down as follows; ...
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... ADRF6702 Control Bits Control Bits DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 ID0 ID0 C3(0) C3(0) C2(0) C2(0) C1(0) C1(0) Divide Ratio Divide Ratio 21 21 Integer mode Integer mode nly) nly ...
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... ADRF6702 DB23 DB23 DB22 DB21 DB22 DB21 DB20 DB19 DB20 DB19 DB18 DB17 DB16 DB18 DB17 DB16 FD10 FD10 FD9 FD9 REGISTER 2—FRACTIONAL DIVIDE CONTROL With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in figure 41 ...
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... This allows a broader range of reference frequency selections while keeping the reference frequency applied to the PFD within an acceptable range. The ADRF6702 also provides a MUXOUT pin that can be programmed to output a selection of several internal signals. The default mode is to provide a lock-detect output to allow the user to verify when the PLL has locked to the target frequency ...
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... ADRF6702 Input Input Output Mux Source Output Mux Source Reference Reference Path Source Path Source DB23 DB23 DB22 DB22 DB21 DB21 DB20 DB20 DB19 DB19 DB18 DB18 DB17 DB17 RMS2 RMS2 RMS1 RMS1 RMS0 RMS0 RS1 RS1 RS0 RS0 CPM CPM ...
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... Disable Disable 1 1 Enable (default) Enable (default) MBE MBE Mod Bias Enable Mod Bias Enable 0 0 Disable Disable Enable Enable default) default) ADRF6702 R5:DB4(LXL Control Bits Control Bits DB2 DB2 DB1 DB1 DB0 DB0 C3(1) C3(1) C2(0) C2(0) C1(1) C1(1) LO Output LO Output Driver Enable ...
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... ADRF6702 REGISTER 6 VCO CONTROL AND ENABLES With R6[2:0] set to 110, the VCO Control and Enables register is programmed as shown in figure 16. VCO band selection is normally selected based on BANDCAL calibration, though the user can directly select the VCO band using register 6. The VCO BS SRC determines whether the ...
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... Figure 12. VCO Control and Enable (R7) Rev. PrE | Page DB9 DB9 DB8 DB8 DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 ADRF6702 Control Bits Control Bits DB2 DB2 DB1 DB1 DB0 DB0 C3(1) C3(1) C2(1) C2(1) C1(1) C1(1) ...
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... SEATING PLANE Figure 13. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Table 7. Ordering Guide Model Temperature Range (°C) ADRF6702ACPZ 1 - RoHS Compliant Part ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...