ICM7211A Intersil Corporation, ICM7211A Datasheet
ICM7211A
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ICM7211A Summary of contents
Page 1
... ROM or CPU time for decoding and display updating. The ICM7211AM provides the “Code B” output code, i.e., 0-9, dash blank, but will correctly decode true BCD to seven-segment decimal outputs. Ordering Information ...
Page 2
... Pinouts ICM7211AM (PDIP) TOP VIEW OSC CHIP SELECT CHIP SELECT DIGIT ADRESS BIT DIGIT ADRESS BIT ...
Page 3
... Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than V destructive device latchup. For this reason recommended that no inputs from external sources not operating on the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211AM be turned on first. 2. θ ...
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... Chip Select 2 34 Timing Diagram CS1 (CS2) CS2 (CS1) DATA AND DIGIT ADDRESS 4 ICM7211AM ICM7211AM are considered to be normal operating input logic levels. Actual input low and high levels are specified SS CONDITIONS V = Logical One Ones (Least Significant Logical Zero Logical One ...
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... DISPLAY BLANK, PIN 36 OPEN 25° (V) SUPP FIGURE 2. OPERATING SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 5 ICM7211AM ICM7211AM T = -20° 70° FIGURE 3. BACKPLANE FREQUENCY AS A FUNCTION OF 180 T = 25°C A 150 C = 0pF OSC (PIN 36 OPEN) ...
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... SEGMENTS . This allows SS Input Configurations and Output Codes The ICM7211AM accepts a four-bit true binary (i.e., positive level = logical one) input at pins 27 thru 30, least significant bit at pin 27 ascending to the most significant bit at pin 30. It decodes the binary input into seven-segment alphanumeric “Code B” output, i.e., 0-9, dash blank. These codes are shown explicitly in Table 1 ...
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... The ICM7211AM is intended to accept data from a data bus under processor control. In these devices, the four data input bits and the two-bit digit address (DA1 pin 31, DA2 pin 32) are written into input buffer latches when both chip select inputs (CS1 pin 33, CS2 ...
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... SEGMENTS 6- 37-40 DATA B0-B3 36 OSC DS1 DS2 CS1 I I/O FIGURE 7. 80C48 MICROPROCESSOR INTERFACE 8 DIGIT LCD DISPLAY ICM7211AM LOW ORDER DIGITS SEGMENTS 6- 37-40 DATA 36 OSC B0-B3 CS2 DS1 DS2 CS1 CS2 ...