ICM7216A Intersil Corporation, ICM7216A Datasheet - Page 11

• Manufacturer Part Number: ICM7216A
• Description: 8-digit, Multi-function, Frequency Counters/timers
• Manufacturer: Intersil Corporation

Time Interval Measurement
When in the time interval mode and measuring a single
event, the lCM7216A and lCM7216B must first be “primed”
prior to measuring the event of interest. This is done by first
generating a negative going edge on Channel A followed by a
negative going edge on Channel B to start the “measurement
interval”. The inputs are then primed ready for the measure-
ment. Positive going edges on A and B, before or after the
priming, will be needed to restore the original condition.
Priming can be easily accomplished using the circuit in
Figure 13.
Following the priming procedure (when in single event or 1
cycle range) the device is ready to measure one (only)
event.
When timing repetitive signals, it is not necessary to “prime”
the lCM7216A and lCM7216B as the first alternating signal
states automatically prime the device. See Figure 1.
During any time interval measurement cycle, the ICM7216A
and lCM7216B require 200ms following B going low to
update all internal logic. A new measurement cycle will not
take place until completion of this internal update time.
Oscillator Considerations
The oscillator is a high gain CMOS inverter. An external
resistor of 10M to 22M should be connected between the
OSCillator INPUT and OUTPUT to provide biasing. The
oscillator is designed to work with a parallel resonant 10MHz
quartz crystal with a static capacitance of 22pF and a series
resistance of less than 35 .
For a specific crystal and load capacitance, the required g
can be calculated as follows:
g
where C
N.O.
FIGURE 13. PRIMING CIRCUIT, SIGNALS A AND B BOTH HIGH
M
V
V
=
DD
SS
100K
2
L
PRIME
C
DEVICE
=
1
IN
OR LOW
-------------------------------- -
C
1
2
C
C
1N914
IN
OUT
IN
+
C
C
V
V
OUT
SIGNAL A
SIGNAL B
R
SS
OUT
DD
CD4049B Inverting Buffer
CD4070B Exclusive - OR
S
150K
0.1 F
1
+
1
C
------- -
C
O
L
2
TYPE
1
ICM7216A, ICM7216B, ICM7216D
10K
2
2
V
SS
10nF
INPUT A
INPUT B
1
M
9-20
C
R
C
C
The required g
for the lCM7216 to insure reliable startup. The OSCillator
INPUT and OUTPUT pins each contribute about 5pF to C
and C
C
static capacitance.
In cases where non decade prescalers are used it may be
desirable to use a crystal which is neither 10MHz or 1MHz.
In that case both the multiplex rate and time between mea-
surements will be different. The multiplex rate is
the 1MHz mode. The time between measurements is
The crystal and oscillator components should be located as
close to the chip as practical to minimize pickup from other
signals. Coupling from the EXTERNAL OSClLLATOR INPUT
to the OSClLLATOR OUTPUT or INPUT can cause undesir-
able shifts in oscillator frequency.
Display Considerations
The display is multiplexed at a 500Hz rate with a digit time of
244 s. An interdigit blanking time of 6 s is used to prevent
display ghosting (faint display of data from previous digit
superimposed on the next digit). Leading zero blanking is
provided, which blanks the left hand zeroes after decimal
point or any non zero digits. Digits to the right of the decimal
point are always displayed. The leading zero blanking will be
disabled when the Main Counter overflows.
The lCM7216A is designed to drive common anode LED
displays at peak current of 25mA/segment, using displays
with V
3mA under these conditions. The lCM7216B and lCM7216D
are designed to drive common cathode displays at peak cur-
rent of 15mA/segment using displays with V
15mA. Resistors can be added in series with the segment
drivers to limit the display current in very efficient displays, if
required. The Typical Performance Curves show the digit
and segment currents as a function of output voltage.
To get additional brightness out of the displays, V
increased up to 6.0V. However, care should be taken to see
that maximum power and current ratings are not exceeded.
The segment and digit outputs in lCM7216s are not directly
compatible with either TTL or CMOS logic when driving
LEDs. Therefore, level shifting with discrete transistors may
be required to use these outputs as logic signals.
2 10
------------------ -
f
MUX
f
O
S
IN
OUT
OUT
OSC
= 2 f
= Crystal Series Resistance
= Crystal Static Capacitance
= Input Capacitance
6
F
=
= Output Capacitance
OUT
should be approximately twice the specified crystal
in the 10MHz mode and
= 1.8V at 25mA. The average DC current will be over
------------------ -
2 10
f
OSC
. For maximum stability of frequency, C
4
M
should not exceed 50% of the g
for 10MHz mode and
2 10
------------------ -
f
OSC
5
in the 1MHz mode.
f
MUX
=
F
M
------------------ -
2 10
DD
= 1.8V at
f
OSC
specified
may be
IN
3
and
for
IN