IR3513Z International Rectifier Corp., IR3513Z Datasheet
IR3513Z
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IR3513Z Summary of contents
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... DESCRIPTION The IR3513Z Control IC provides overall control of a scalable number of phases along with an internal gate driver, current sense/sharing, and PWM. This allows the IR3513Z to implement a stand-alone single-phase regulator or interface with additional Phase ICs to develop a power solution with any number of phases. With this arrangement, the final solution requires only 1 IC per phase to deploy phases. Other approaches require a control IC plus driver ICs or scalable “ ...
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... ORDERING INFORMATION Device IR3513ZMTRPBF * IR3513ZMPBF • Samples only PIN DESCRIPTION PIN# PIN SYMBOL 1 GATEH High-side driver output and input to GATEL non-overlap comparator. 2 BOOST Supply for high-side driver. An internal bootstrap synchronous PFET is connected between this pin and the VCCP pin. 3 VCCP Supply for low-side driver. An internal bootstrap synchronous PFET is connected from this pin to the BOOST pin ...
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... Output of the VCCL regulator error amplifier to control an external transistor. The pin senses the input of the power supply through a resistor at power-up. 31 VCC Power Input for under voltage lockout (UVLO) detection and supply for internal IC circuits Return for high-side driver and reference for GATEL non-overlap comparator. Page 3 IR3513Z May 11, 2009 ...
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... DC, -5V 3A for 100ns, 100mA DC for 100ns IR3513Z I SINK 3A for 100ns, 100mA DC 3A for 100ns, 100mA DC 5A for 100ns, 200mA DC 5A for 100ns, 200mA DC n/a 1mA 1mA 5mA 1mA 20mA 1mA 1mA 1mA 25mA 25mA ...
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... KΩ OSC R =7.75 KΩ OSC I(PHSOUT)= -1mA I(PHSOUT)= 1mA Compare to V(VCCL) ENABLE rising ENABLE falling 0V ≤ V(ENABLE) ≤ 3.3V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 IR3513Z ≤ T ≤ 125 C, J ≤ 50.0 KΩ 0.1µF +/- OSC SS/DEL MIN TYP ...
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... VOSEN+ Input Voltage Range V(VCCL)=7V High Voltage V(VCCL) – V(VO) Low Voltage V(VCCL)=7V Page 6 TEST CONDITION MIN -70 -5% -10 0.50 35 0.75 - 3.0 -0 IR3513Z TYP MAX UNIT -40 -10 mV 605 +5% µA / Rosc(kΩ ) 4096 Cycle 2048 Cycle 1024 Cycle 1.00 1.75 mA 2.00 3.00 kHz ...
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... VCC Under Voltage Lockout Comparator (UVLO) Start Threshold Stop Threshold Hysteresis Start – Stop Page 7 TEST CONDITION MIN 1.0 0.9 0 2.8 125 -1 -1 100 20 7 0.40 5 500 100 2.7 -640 -18.5 5 6.9 6.5 350 IR3513Z TYP MAX UNIT 2.2 3.5 ms 1.5 4.5 ms 1.3 3.8 ms 125 300 us 1.4 1 µ µ µA/µ 120 ...
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... GATEL falling GATEH rising to 1V GATEH low to GATEL high BOOST = VCCP = 7V PGND = delay 0V, measure time from GATEH falling GATEL rising to 1V Disable Pull-Down Resistance Ta=25 Page 8 TEST CONDITION o C Note 1 IR3513Z MIN TYP MAX UNIT 150 200 250 ...
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... VCCL = 5V. Measure time from EAOUT < V(VREF) (200mV overdrive) to GATEL transition to < 4V. Page 9 TEST CONDITION MIN -200 -50 -1 30.5 4.8 -10 -5 -0.2 2.3 2.9 3.6 500 500 - -230 -225 -315 40 20 IR3513Z TYP MAX UNIT mV/ 52 160 ns 0 200 33.0 35.5 V/V 6.8 8.8 MHz 6 V/µ ...
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... Apply step voltage to V(CSIN+) – V(CSIN-). Measure time to V(GATEL)< 1V. I(BOOST) = 30mA, 6V ≤ VCCL ≤ 7V Compare to V(VCCL) I(PG) = 4mA V(PG) = 5.5V I(PG)=4mA, V(PG)<300mV V(VCC) – V(VOUT) > 2.5V V(VCCP)=7V, V(BOOST)=7V 4V ≤ V BOOST) ≤ 30V ( Measured in the application IR3513Z MIN TYP MAX UNIT - 200 ...
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... IOCSET IROSC ROSC BUFFER AMPLIFIER CURRENT 0.6V SOURCE + GENERATOR - REMOTE SENSE AMPLIFIER 50K 50K + - 50K 50K Figure 2 - System Set Point Test Circuit IR3513Z EAOUT 1k FB VREF OCSET RVREF CVREF LGND RROSC ROSC VOUT SYSTEM EAOUT SET POINT VOLTAGE VOSEN+ VOSNS- VOSEN- May 11, 2009 ...
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... A voltage-type error amplifier with high-gain (110dB) and wide-bandwidth is used for the control loop not unity gain stable. The power-stage input voltage is sensed by the IR3513Z, and optional phase ICs, to provide feed-forward control. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage ...
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... The inductor current will increase much more rapidly than decrease in response to load transients. An additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VREF. Figure 5 depicts PWM operating waveforms under various conditions. Page 13 Figure 4 - Five Phase Oscillator Waveforms IR3513Z May 11, 2009 ...
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... Page 14 Figure 5 - PWM Operating Waveforms − MAX MIN T SLEW V O − MAX MIN T SLEW + BODYDIODE + IR3513Z BODYDIODE the two time constants match, the L May 11, 2009 . The ...
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... Current Sense Amplifier A high speed differential current sense amplifier is included in both the IR3513Z and optional phase ICs, as shown in Figure 6. Its gain is nominally 33 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path ...
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... IR3513Z THEORY OF OPERATION Block Diagram The IR3513Z Block diagram is shown in Figure 7, and specific features are discussed in the following sections. ENABLE COMPARATOR ENABLE - 250nS + BLANKING 850mV 800mV VCCLDRV 80mV VCCL REGULATOR 120mV AMPLIFIER VCCLFB 3. 0.94 1.19V VCCL OUTPUT 0.86 COMPARATOR + - VCC SS/DEL 1.425V + VREF=0.84V - 2 ...
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... The actual VREF voltage does not determine the system accuracy, which has a wider tolerance. The IR3513Z can accept changes in the MARGIN input while operating and vary the VREF voltage accordingly. The slew rate of the voltage at the VREF pin can be adjusted by an external capacitor between VREF pin and LGND pin. A resistor connected in series with this capacitor is required to compensate the VREF buffer amplifier ...
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... If an over-current condition is again encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. Page 18 SOFT START PG DELAY TIME TIME Figure 8 - Start-up sequence IR3513Z NORMAL OPERATION May 11, 2009 ...
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... Figure 9 - Constant over-current control waveforms during and after soft start Linear Regulator Output (VCCL) The IR3513Z has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear regulator. The output voltage can be programmed between 4.75V and 7V by the resistor divider at VCCLFB pin. The regulator output powers the gate drivers of the phase ICs and circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency ...
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... VCCL Under Voltage Lockout (UVLO) The IR3513Z IC monitors both the Vcc and VCCL for under voltage condition. During power up, the fault latch will be reset if VCCL is above 94% (typical) of the voltage set by resistor divider at VCCLFB pin and the VCC exceeds 7.5V (typical). If VCCL voltage drops below 86% (typical) of the set value or VCC drops below 7V (typical), the fault latch will be set ...
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... IIN (ISHARE) GATEH GATEL FAULT LATCH ERROR AMPLIFIER VREF OUTPUT (EAOUT) NORMAL OPERATION Figure 11 Over-voltage protection during normal operation 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OVSN VCCL UVLO ROSC/OVP 1.6V Figure 12 - Over-voltage protection during power-up Page 21 IR3513Z AFTER OVP CONDITION OVP May 11, 2009 ...
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... Figure 17, the converter will soft start until SS/DEL voltage is above 3.92V (4.0V-0.08V). Then, over voltage comparator is activated and fault latch is set. 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) 1.73V VCCL UVLO ROSC/OVP 1.6V Figure 13 - Over-voltage protection with pre-charging converter output Vo > 1.73V Figure 14 - Over-voltage protection with pre-charging converter output VREF + 0.13V <Vo < 1.73V Page 22 IR3513Z May 11, 2009 ...
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... Output Voltage Under-voltage Monitoring The IR3513Z compares the FB pin to a voltage, V, equal to 0.897×Vref. If the FB pin is 50mV (typical) below the aforementioned V, the output voltage under-voltage monitor will trigger, pulling the PG pin low. The output voltage under-voltage monitor does not effect switching of the phases or soft start. ...
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... The rest of the faults (except for UVLO Vout) are latched in the SS fault latch and do not need to recycle the VCCL power in order for IR3513Z to resume operation. IR3513Z will automatically resume operation when these fault conditions no longer apply in the system. Most of the faults disable the error amplifier (EA) and discharge the soft start capacitor ...
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... APPLICATIONS INFORMATION Figure 15 - Scalable Master (IR3513Z) & Slave (IR3505Z) POL modules with programmable output voltage and Page 25 redundant OVP sense May 11, 2009 IR3513Z ...
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... IR3513Z EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3513Z generates square-wave pulses to synchronize the phase ICs. The switching frequency of the each phase converter equals the PHSOUT frequency, which is set by the external resistor R curve in Figure 16. The CLKOUT frequency equals the switching frequency multiplied by the phase number. ...
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... 600 Ω and R FB3 * − IR3513Z ) and room temperature L_MAX ( ROOM (6) is the required over current LIMIT and is determined OSC ( OCSET (8) (9) (10) May 11, 2009 CS_OFST) ...
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... VCCL (min) < VCCLDRV ( max) is the minimum and maximum anticipated input voltage. If the above I min and Resistor Pre-select the capacitor C L IR3513Z (11) (12) VCCL _ C (13) (14) or Darlington configuration can be used and capacitor C CS and calculate R CS (15) May 11, 2009 CS as ...
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... Rcp Page 29 OV2 is calculated based on (16). R OV1. OV2 * − VOVSNS and Resistor R VREF VREF − 132 * 10 = SINK SR MARGIN MARGIN − ∗ VREF IR3513Z (16) as defined in (17), where VREF (17) (18) (19) (20) (21) (22) May 11, 2009 ...
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... ⋅ Rst Rc ) ⋅ ⋅ + ⋅ − ⋅ ⋅ + ⋅ ⋅ IR3513Z (23) (24) (25) (26) (27) ) (28) (29) (30) (31) (32) (33) (34) − (35 (36) May 11, 2009 ...
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... Rf b2 Vout Figure 17 Voltage Loop Compensation Network Page 31 Ccp1 Cf b Ccp Rcp EAout - Vref IR3513Z May 11, 2009 ...
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... Place the IC, gate drive side as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of the gate drive paths. • Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. • Page 32 and C ) close to IC. Use Kelvin connection for the inductor CS CS • IR3513Z May 11, 2009 ...
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... Four 0.30mm diameter vias shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. • No PCB traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can cause the IC to rise up from the PCB resulting in poor solder joints to the IC leads. Page 33 IR3513Z May 11, 2009 ...
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... Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The four vias in the land pad should be tented or plugged from bottom board side with solder resist. Page 34 IR3513Z May 11, 2009 ...
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... The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page 35 IR3513Z May 11, 2009 ...
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... JC Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. Visit us at www.irf.com for sales contact information. www.irf.com IR3513Z o = 0.86 C/W TAC Fax: (310) 252-7903 May 11, 2009 ...