IR3094M International Rectifier Corp., IR3094M Datasheet
IR3094M
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IR3094M Summary of contents
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... Separate OVP sense line to sense the output voltage and latched OVP with protection x Inductor DCR sensing for current sensing will support up to 5.1V output applications x Available 48L MLPQ package ORDERING INFORMATION Device IR3094MTRPBF IR3094MPBF PACKAGE INFORMATION Page PHASE PWM CONTROLLER FOR POINT OF LOAD NC GATEH1 NC PGND1 ...
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PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 NC Not connected 2 NC Not connected 3 ROSC Connect a resistor to VOSNS- to program oscillator frequency, OCSET and STBIAS bias currents. 4 VOSNS- Remote Sense Input. Connect to ground at ...
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ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..0 Storage Temperature Range………………….-65 PIN NAME VMAX 3 ROSC 20V 4 VOSNS- 0.5V 5 OCSET 20V 6 VDAC 20V 7 VDRP 20V 8 FB 20V 9 EAOUT 10V 10 SS/DEL 20V 11 SCOMP2 20V 12 ...
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ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8 28V, C =3.3nF, C CCHX GATEHX PARAMETER VREF Reference Sink Current Source Current System Reference Voltage Error Amplifier Input Offset Voltage UVL FB Bias Current UVL Head Room ...
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PARAMETER BIASOUT Regulator SETBIAS Bias Current R Set Point Accuracy V(SETBIAS)-V(BIASOUT) @ 100mA I(BIASOUT)=100mA,Threshold when BIASOUT Dropout Voltage V(SETBIAS)-V(BIASOUT)=0.45V BIASOUT Current Limit Soft Start and Delay SS/DEL to FB Input Offset With FB = 0V, adjust V(SS/DEL) until Voltage EAOUT ...
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PARAMETER Enable Input Threshold Input Resistance Pull-up Voltage Gate Drivers GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time High Voltage (AC) Low Voltage (AC) GATEL low to GATEH high delay GATEH low to GATEL high delay ...
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PARAMETER Share Adjust Error Amplifier Input Offset Voltage MAX Duty Cycle Adjust Ratio MIN Duty Cycle Adjust Ratio Transconductance SCOMPX Source/Sink Current SCOMPX Precondition and GATELX Release Threshold SCOMP precondition current Duty Cycle Match at Startup 0% Duty Cycle Comparator ...
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TYPICAL OPERATING CHARACTERISTICS I(VDAC) Sink and Source Currents vs. ROSC REF 180 160 140 120 100 ROSC in Kohms Oscillator freq vs. ROSC 500 450 400 350 300 ...
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Peak Low side Gate drive current vs. Laod capacitance 3.250 3.000 2.750 2.500 2.250 2.000 1.750 1.500 1.250 1.000 C(GATELX Error Amplifier Frequency Response 180 100 0 93dB DC gain 88° Phase Margin ...
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ROSC VCC LGND UVL - 4 X IROSC + SETBIAS 1.243 7.5V START 7.0V STOP IROSC BIASOUT CLK1 UVL 5VUVL CLK2 - CLK3 + 4.36V START 4.17V STOP Oscillator PWRGD OVER CURRENT OCSET - IAVE + IROSC DELAY + - ...
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PWM Operation The IR3094 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage control ...
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INTERNAL OSCILLATOR RAMP DUTY CYCLE CLK1 CLK2 CLK3 EAOUT 0.6V RAMP1 SLOPE = 50mV / % DC The RSFF is reset dominant allowing both phases zero duty cycle within a few tens of nanoseconds in response ...
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Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased more. This patent pending technique is referred to as “body braking” and is accomplished through ...
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Power-up in Non-Synchronous Mode The SYNC LATCH is set by either a UVLO or a Low Enable fault at the beginning of the power-up cycle, keeping all three low side gate drivers low. The SYNC LATCH is then reset once ...
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APPLICATIONS INFORMATION OVP ENABLE VOUT+ C5VREF RROSC RFB NC NC RREF ROSC ROCSET VOSNS- CREF OCSET VREF RDRP VDRP FB EAOUT SS/DEL RCOMP CCOMP SCOMP2 SCOMP3 CSC3 CSC2 Cosns- CSS RSC3 VIN RSC2 VIN RSET CVCC CVIN GND PGOOD Oscillator ...
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VCC Under Voltage Lock Out 2. 5VUVL Under Voltage Lock Out 3. Low Enable pin 4. Over Current condition. A delay is included if any of the four fault conditions occurs after a successful soft start sequence. This is ...
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Once C is chosen, the soft start delay time SS t time from output voltage (V VccPG respectively. VREF Compensation Network network tied between VREF pin and VOSENS- is needed to compensate VREF circuit. VREF should come ...
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MAX The current sense amplifier gain of IR3094 decreases with temperature at the rate of 1400 PPM, which compensates part of the inductor DCR increase. The minimum current sense amplifier gain at the maximum IC temperature T ...
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The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can ...
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Master-Slave Current Share Loop Current sharing between phases of the converter is achieved by a Master-Slave current share loop topology. The output of the Phase 1 Current Sense Amplifier sets the reference for the Share Adjust Error Amplifiers. Each Share ...
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RCP RFB VO VREF VDAC RDRP VDRP a) Type II compensation ( Figure 9. Voltage loop compensation networks Type II Compensation for Voltage Droop Applications Determine the compensation at no load, the worst case condition. Choose the crossover ...
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DRP R and C have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency CP CP and transient load response. Determine ...
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MathCAD file to estimate the power dissipation of the IC The full featured Control IC IR3094 contain both Control and 3 phase Gate Drive functions. It also has the adjustable voltage bias regulator inside to provide MOSFET Drive Voltage. For ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Refer to the schematic in Figure 6 – System Diagram. x Dedicate at ...
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PCB AND STENCIL DESIGN METHODOLOGY x 7x7 x 48 Lead x 0.5mm pitch MLPQ See Figures 10-12. PCB Metal Design (0.5mm Pitch Leads) 1. Lead land width should be equal to nominal part lead width. The minimum lead to lead ...
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Figure 10. PCB metal and solder resist. Page IR3094PBF 09/26/05 ...
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Figure 11. PCB metal and component placement. Page IR3094PBF 09/26/05 ...
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Page Figure 12. Stencil design. IR3094PBF 09/26/05 ...
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PACKAGE DIMENSIONS IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 Page Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification ...