IR3505M International Rectifier Corp., IR3505M Datasheet
IR3505M
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IR3505M Summary of contents
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DESCRIPTION The IR3505 Phase IC combined with an IR XPhase3 implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and ...
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... ORDERING INFORMATION Part Number IR3505MTRPBF * IR3505MPBF * Samples only ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature… ...
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RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 8.0V ≤ V ≤ 16V, 4.75V ≤ CCL o o ≤1.5MHz ≤ T ≤ 125 C J ELECTRICAL CHARACTERISTICS The electrical characteristics involve the spread of values guaranteed ...
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PARAMETER PWM Comparator PWM Ramp Slope Vin=12V Input Offset Voltage Note 1 EAIN Bias Current 0 ≤ EAIN ≤ 3V Minimum Pulse Width Note 1 Minimum GATEH Turn-off Time Current Sense Amplifier CSIN+/- Bias Current CSIN+/- Bias Current Note 1 ...
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PARAMETER OVP Comparator OVP Threshold Propagation Delay Synchronous Rectification Disable Comparator Threshold Voltage Negative Current Comparator Input Offset Voltage Propagation Delay Time Bootstrap Diode Forward Voltage Debug Comparator Threshold Voltage General VCC Supply Current VCCL Supply Current BOOST Supply Current ...
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PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 ISHARE Output of the Current Sense Amplifier is connected to this pin through a 3k resistor. Voltage on this pin is equal to V(DACIN) + 32.5 [V(CSIN+) – V(CSIN-)]. Connecting all ISHARE ...
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SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the XPhase trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. Input voltage is ...
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Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...
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Figure 4 Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...
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IR3505 THEORY OF OPERATION Block Diagram The Block diagram of the IR3505 is shown in Figure 5, and specific features are discussed in the following sections. CLKIN PHSIN 100% DUTY LATCH PWMQ CLK Q PWM_CLK PWM_CLK D PWM COMPARATOR EAIN ...
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Over Voltage Protection (OVP) The IR3505 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an ...
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Emulated Bootstrap Diode IR3505 integrates a PFET to emulate the bootstrap diode. An external bootstrap diode connected from VCCL pin to BOOST pin can be added to reduce the drop across the PFET but is not needed in most applications. ...
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Figure 7 provides an application circuit that allows adjustment to the number of phases. By populating zero ohm jumpers, or not; the number of phases can be adjusted by diverting the daisy chain timing from a 3505 to the next ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane, which is ...
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PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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Solder Resist • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 16L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page C/W, θ JA Data and specifications subject ...