IR3082M International Rectifier Corp., IR3082M Datasheet
IR3082M
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IR3082M Summary of contents
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XPHASE DESCRIPTION The IR3082 Control IC combined with an IR XPhase to implement a complete Opteron or Athlon64 power solution. The “Control” IC provides overall system control and interfaces with any number of “Phase ICs” which each drive and monitor ...
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... ORDERING INFORAMATION IR3082MTR * IR3082M * Samples only ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150 Storage Temperature Range………………….-65 ESD Rating………………………………………HBM Class 1C JEDEC standard ...
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ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 9.6V ≤ ≤ T ≤ 100 C, ROSC = 24KΩ, CSS/DEL = 0.1µF +/-10% J PARAMETER VDAC Reference System Set-Point Accuracy (Deviation from Table 1 per ...
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PARAMETER Soft Start and Delay Start Delay (See Fig 10) Soft Start Time (See Fig 10) PWRGD Delay (See Fig 10) OC Delay Time SS/DEL to FB Input Offset Voltage Charge Current Discharge Current Charge/Discharge Current Ratio OC Discharge Current ...
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VDAC - PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1-5 VID4-0 Inputs to VID Converter. 6 VOSNS- Remote Sense Input. Connect to ground at the Load. 7 ROSC Connect a resistor to VOSNS- to program ...
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SYSTEM THEORY OF OPERATION TM Architecture XPhase TM The XPhase architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current, and fast transient response. The architecture can be ...
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PWM Control Method The PWM block diagram of the XPhase trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the ...
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VPEAK (5.0V) ) VPHASE4&5 (4.5V VPHASE3&6 (3.5V VPHASE2&7 (2.5V VPHASE1&8 (1.5V VVALLEY (1.00V ...
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TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The slew rate of the inductor current can be significantly increased by ...
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The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can ...
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IR3082 THEORY OF OPERATION Block Diagram The Block diagram of the IR3082 is shown in figure 7 and discussed in the following sections. VCC - + + VCC UVLO 9.75V COMPARATOR 9.0V - ENABLE ENABLE - COMPARATOR + + + ...
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Adaptive Voltage Positioning Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in Figure ...
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The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin ...
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Remote Voltage Sensing To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related ...
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Over Current Protection (OCP) The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage, which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the ...
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VCC (12V) 1.27V ENABLE (VTT) 3.83V SS/DEL 1.3V VOUT PWRGD START START DELAY (ENABLE ENDS 1.9ms FAULT MODE) VCC (12V) ENABLE 3.83V SS/DEL 1.3V VOUT PWRGD IOUT START-UP NORMAL OPERATION (ENABLE GATES (VOUT CHANGES DUE TO FAULT MODE) LOAD AND ...
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APPLICATIONS INFORMATION 12V RVCC 10 ohm CVCC 0.1uF ENABLE S R 0.1uF ...
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PERFORMANCE CHARACTERISTICS Figure 13 - Oscillator Frequency vs. ROSC 1050 950 850 750 650 550 450 350 250 150 ROSC (KOhm) Figure 15 - VDAC Source and Sink Currents vs. ROSC 250 230 210 190 ...
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DESIGN PROCEDURES – IR3082 AND IR3086 CHIPSET IR3082 EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3082 generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which ...
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DEL t SSDEL VDAC Slew Rate Programming Capacitor C The slew rate of VDAC down-slope SR Equation (7), where I is the sink current of VDAC pin as shown in Figure 15. The resistor R ...
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No Load Output Voltage Setting Resistor R A resistor between FB pin and the converter output is used to create output voltage offset V difference between V voltage and output voltage at no load condition. Adaptive voltage positioning lowers the ...
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not used, R should be chosen so that the offset voltage is small enough. Usually R CS- CS+ than 2 kΩ and therefore a larger C Over Temperature Setting Resistors R The threshold voltage of VRHOT comparator ...
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RA = PHASEx R PHASEx HOTSET R PHASEx 3 V BIAS If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS times RA connect HOTSET pin between R R respectively. Pre-select ...
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Type II Compensation Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the output ...
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DESIGN EXAMPLE ― 5-PHASE OPTERON CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.3 V DAC No Load Output Voltage Offset: V Maximum Output Current: I OMAX Output Impedance: R =0.75 mΩ O Soft Start Time: t ...
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From Figure 15, the source current of VDAC pin is 170uA. The VDAC up-slope slew rate is − ⋅ 170 SOURCE − UP ⋅ VDAC ...
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IR3086 EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C RAMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R ⋅ ⋅ ⋅ PWMRMP [ln PWMRMP . − ...
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VOLTAGE LOOP COMPENSATION All ceramic output capacitors are used in the design, type III compensation as shown in Figure 18(b) is used here. Choose the desired crossover frequency fc =80 kHz and determine Rcp and C π ⋅ ⋅ ⋅ ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane LGND. • ...
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METAL AND SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are ...
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PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 20L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page C/W, θ C/W JA ...