CYP15G0101DXB Cypress Semiconductor Corporation., CYP15G0101DXB Datasheet
CYP15G0101DXB
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CYP15G0101DXB Summary of contents
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... CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices. ...
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... Repetitions of 19 ones followed by 1 zero or 19 zeros fol- lowed by 1 one. x10 x11 Phase Elasticity Align Buffer Buffer Encoder Decoder 8B/10B 8B/10B Framer Serializer Deserializer RX TX CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB serial links. Some applications include backplanes on switches, routers, Page [+] Feedback ...
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... RFEN RFMODE DECMODE RXRATE RXMODE RXCKSEL Document #: 38-02031 Rev. *J Bit-Rate Clock Transmit Mode BIST Enable Latch Latch Clock Select CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB = Internal Signal TRSTZ Character-Rate Clock 10 OUT1+ OUT1– OUT2+ OUT2– TXLB 2 4 Output Enable OELE Latch BISTLE ...
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... OELE GND GND GND RXST[0] GND GND GND RXD[5] TXD[6] TXCT[1] LFI RXD[6] TXD[5] TXCT[0] RXCLK– RXD[7] TXD[4] TXD[7] RXCLK CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB OUT1– [2] #NC OUT1 PARCTL RFMODE INSEL TMS TRSTZ TDI TCLK RXCKSEL TXCKSEL TXPER REFCLK– ...
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... TXCLK↑ is captured relative to TXCLK↑. [3] or REFCLK↑ Note: 3. When REFCLK is configured for half-rate operation (TXRATE of REFCLK. Document #: 38-02031 Rev HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Page [+] Feedback ...
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... The LOW level is usually implemented by direct connection to V not connected or allowed to float, a 3-Level select input will self-bias to the MID level. Document #: 38-02031 Rev TXLOCK (ground). The HIGH level is usually implemented by direct connection CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB [3] (power). When CC Page [+] Feedback ...
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... Receive Operating Mode. This input selects one of two RXST channel status reporting modes and is only interpreted when the Decoder is enabled (DECMODE ≠ LOW). See static control input Table 12 for details. Document #: 38-02031 Rev the serial bit-rate) or character rate (1/10 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB th the serial bit-rate) of the data being Page [+] Feedback ...
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... Serial Rate Select. This input specifies the operating bit-rate range of both transmit and static control input receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH = 800–1500 MBaud (800–1540 MBaud for CYW15G0101DXB). When SPDSEL=LOW, setting TXRATE=HIGH (Half-rate Reference Clock) is invalid. Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Page [+] Feedback ...
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... BOE[1:0] are captured in the internal Output Enable Latch. The specific mapping of BOE[1:0] signals to transmit output enables is listed in Table 8. If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable both outputs. Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Page ...
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... Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not LVTTL Output selected. TDI LVTTL Input, Test Data In. JTAG data input port. internal pull-up Power V +3.3V power CC GND Signal and power ground for all internal circuits Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Page [+] Feedback ...
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... ODD parity PARCTL = HIGH with the Encoder enabled (or MID with the Encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are checked for ODD parity along with the TXOP bit. When PARCTL = LOW, parity checking is disabled. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB on both edges of REFCLK ...
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... TXD[7:0] and TXCT[1:0] inputs is passed directly to the Transmit Shifter without modification. If parity checking is enabled (PARCTL ≠ LOW) and a parity error is detected, the 10-bit character is replaced with the 1001111000 pattern (+C0.7 character) regardless of the running disparity of the previous character. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB ESCON and FICON™ ...
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... TXCT[1:0] ≠ 00, the Word Sync Sequence is terminated, and a character representing the data and control bits is generated by the Encoder. This resets the Word Sync Sequence state machine such that it will start at the beginning of the sequence at the next occurrence of TXCT[1:0] = 11. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Characters Generated Page ...
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... Word Sync Sequence. For the sequence to be started, the TXCT[1:0] inputs must both be sampled HIGH. The generation and operation of this Word Sync Sequence is the same as that documented for TX Mode 3. Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Transmit BIST The transmit channel contains an internal pattern generator that can be used to validate both device and link operation ...
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... Table 10. The Analog Signal Detect monitor is active for the present Line Receiver, as selected by the INSEL input. When configured for local loop-back (LPEN = HIGH), the Analog Signal Detect Monitor is disabled. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB > 100 mV, or 200-mV DIFFS [10] ...
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... When a disabled receive channel is reenabled, the status of the LFI output and data on the parallel outputs may be indeterminate for ms. Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB When RXLE = HIGH and BOE[0] = HIGH, the receive channel is enabled to receive and recover a serial stream from the Line Receiver ...
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... Received Special Code characters are decoded using the Cypress column of Table 21. When DECMODE = HIGH, the 10-bit transmission characters are decoded using Table 20 and Table 21. Received Special Code characters are decoded using the Alternate column of Table 21. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Page [+] Feedback ...
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... Elasticity Buffer to be centered. The Elasticity Buffer may also be centered by a device reset operation initiated through the TRSTZ input. However, following such an event, the CYP(V)(W)15G0101DXB will normally require a framing event before it will correctly decode characters. CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB clocked relative to ...
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... This can be done Note: 15. The RXOP output is also driven from the Output Register, but its interpretation is under the separate control of PARCTL. Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB by sequencing the appropriate values on the BOE[1:0] inputs while the OELE and RXLE signals are raised and lowered. For ...
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... Receive path parity output driver (RXOP) is disabled (High-Z) when PARCTL 17. When the Decoder is bypassed (DECMODE = LOW) and BIST is not enabled (Receive BIST Latch output is HIGH), RXST[2] is driven to a logic-0, except when the character in the output buffer is a framing character. Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Table 15. Output Register Parity Generation ...
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... Running Disparity Error. The character on the output bus is a C4.7, C1.7, or C2.7. 111 3 RESERVED Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB JTAG Support The CYP(V)(W)15G0101DXB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, only boundary scan is supported. This capability is present only on the LVTTL inputs, LVTTL outputs and the REFCLK± ...
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... Next Character RXST = BIST_COMMAND_COMPARE (001) Match Command Data or Command Data End-of-BIST No State Yes, RXST = BIST_LAST_GOOD (010) No, RXST = BIST_ERROR (110) Figure 2. Receive BIST State Machine CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Receive BIST Detected LOW RX PLL Out of Lock RXST = BIST_DATA_COMPARE (000) Page [+] Feedback ...
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... Min. ≤ V ≤ Max. CC Min. ≤ V ≤ Max. CC Min. ≤ V ≤ Max GND IN 100Ω differential load 150Ω differential load CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB V CC +3.3V ± 5% +3.3V ± 5% Min. Max. Unit 2 0.4 V –20 –100 mA –20 20 µA 2 ...
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... V = 1.4V th ≤ 270 ps (d) CML/LVPECL Input Test Waveform ≤ [26] Over the Operating Range Description requirement still needs to be satisfied. DIFFS = = 3.3V, T 25°C, parallel outputs unloaded, RXCKSEL CC A CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Min. Max. Unit − 1.4 − 0 − 1.4 − 0 ...
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... When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW) could be used to clock the receive data out of the device. Document #: 38-02031 Rev. *J Over the Operating Range (continued) Description and t parameters. This means that at faster character rates the REFCLK duty cycle REFH REFL CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Min. Max. Unit 0.2 1 ...
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... T = 25° 25° − = 12. Hence: Total Jitter ( 14 20) (when RXRATE = HIGH) or 1/(f * 10) (when RXRATE = LOW data is being received, or REF CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Min. Max. Unit [35] 5100 666 ps 60 270 ps 100 500 ps 180 1000 ps 60 ...
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... TXCLK t TXCLKL t TXDS t TXDH t REFCLK t REFL t TREFDS t TREFDH t REFCLK t REFH Note 41 t TREFDS t TREFDH t REFCLK t REFH t TXCLKO t TXCLKOD– Note 42 = HIGH) and data is captured using REFCLK instead of TXCLK clock (TXCKSEL CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB t REFL t TREFDS t REFL = LOW), data Page [+] Feedback ...
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... REFCLK t REFH REFL 42 Note t TXCLKO t TXCLKOD– t REFCLK t REFL t RREFDA t REFDV+ t REFCDV+ Note 44 t REFCLK t REFH t RREFDA t RREFDV t REFDV+ t REFCDV+ Note 44 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB t RREFDV t REFDV– t REFCDV– t REFL t RREFDA t RREFDV t REFDV– t REFCDV– 45 Note Page [+] Feedback ...
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... RXCLK RXD[7:0], RXST[2:0], RXOP Receive Interface Read Timing RXCKSEL = MID RXRATE = HIGH RXCLK+ – RXCLK RXD[7:0], RXST[2:0], RXOP Document #: 38-02031 Rev. *J (continued) t RXCLKP t RXCLKH RXCLKL t RXDV– t RXCLKP t RXCLKH t RXDV– CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB t RXDV+ t RXCLKL t RXDV+ Page [+] Feedback ...
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... G2 RXD[1] LVTTL OUT G3 RXD[5] LVTTL OUT G4 GND GROUND G5 GND GROUND G6 GND GROUND G7 GND GROUND G8 TXOP LVTTL IN PU CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Ball ID Signal Name Signal Type G9 TXCLKO+ LVTTL OUT G10 TXCLKO– LVTTL OUT H1 RXD[0] LVTTL OUT H2 RXD[2] LVTTL OUT H3 RXD[6] LVTTL OUT ...
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... Character is a Data Character (c is set to D, and SC/D = LOW Special Character (c is set to K, and SC/D = HIGH). When c is set the decimal value of Document #: 38-02031 Rev. *J CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB the binary number composed of the bits and A in that order, and the y is the decimal value of the binary number composed of the bits H, G, and F in that order ...
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... Character in which the error occurred. Table 19 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 ...
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... D1.3 011 00001 010010 0101 D2.3 011 00010 110001 0101 D3.3 011 00011 001010 0101 D4.3 011 00100 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 110001 1001 ...
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... D6.5 101 00110 000111 0010 D7.5 101 00111 000110 1101 D8.5 101 01000 100101 0010 D9.5 101 01001 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD− Current RD+ abcdei fghj abcdei fghj 101001 1100 101001 0011 011001 1100 011001 0011 111000 1100 000111 0011 111001 0011 ...
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... D11.7 111 01011 001101 0110 D12.7 111 01100 101100 0110 D13.7 111 01101 011100 0110 D14.7 111 01110 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD− Current RD+ abcdei fghj abcdei fghj 010101 1010 010101 1010 110100 1010 110100 1010 001101 1010 001101 1010 ...
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... D28.7 111 11100 010001 0110 D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Current RD− Current RD+ abcdei fghj abcdei fghj 010111 0001 101000 1110 011011 0001 100100 1110 100011 0111 100011 0001 ...
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... C1.7 (CE1) 111 00001 [57] C2.7 (CE2) 111 00010 [57] C4.7 (CE4) 111 00100 = the specified value between 00 and FF). = CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB [46,47] Current RD− Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 001111 0011 110000 1100 ...
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... Pb-Free 100-ball Grid Array BB100 Pb-Free 100-ball Grid Array BB100 Pb-Free 100-ball Grid Array BB100 Pb-Free 100-ball Grid Array BB100 Pb-Free 100-ball Grid Array 0.15(4X) CYP15G0101DXB CYV15G0101DXB CYW15G0101DXB Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial ...
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... Changed verbiage...Paragraph: Clock/Data Recovery Changed verbiage...Paragraph: Range Control Added Power-up Requirements POT Changed CYP15G0101DXB to CYP(V)15G0101DXB type corresponding to the Video-compliant parts Reduced the lower limit of the serial signaling rate from 200 Mbaud to 195 Mbaud and changed the associated specifications accordingly ...