CYWUSB6935 Cypress Semiconductor Corporation., CYWUSB6935 Datasheet - Page 17

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CYWUSB6935

Manufacturer Part Number
CYWUSB6935
Description
Lr 2.4-ghz Dsss Radio Soc
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Document #: 38-16008 Rev. *D
Bit
7
6
5
4:3
2
1
0
Bit
7
6:0 Channel
Reserved
Reserved
Name
Reserve
d
Name
Reserved
Reg Write Control Enables write access to Reg 0x2E and Reg 0x2F.
MID Read Enable The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F). Enabling
Reserved
PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier.
PA Invert
Reset
7
7
Addr: 0x20
Addr: 0x21
Description
This bit is reserved and should be written with zero.
The Channel register (Reg 0x21) is used to determine the Synthesizer frequency. A value of 2 corresponds to a communication
frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The channels are separated from each
other by 1 MHz intervals.
Limit application usage to channels 2–79 to adhere to FCC regulations. FCC regulations require that channels 0 and 1 and
any channel greater than 79 be avoided. Use of other channels may be restricted by other regulatory agencies. The application
MCU must ensure that this register is modified before transmitting data over the air for the first time.
Reg Write
Control
6
6
Description
This bit is reserved and should be written with zero.
These bits are reserved and should be written with zeroes.
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set high. PA
Output Enable and PA Invert cannot be simultaneously changed.
The Reset bit is used to generate a self-clearing device reset.
the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when reading the contents
of the Manufacturing ID register (Reg 0x3C-0x3F).
1 = Enables write access to Reg 0x2E and Reg 0x2F
1 = Enables read of MID registers
0 = Disables read of MID registers
0 = Reg 0x2E and Reg 0x2F are read-only
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
1 = PACTL active low
0 = PACTL active high
1 = Device Reset. All registers are restored to their default values.
0 = No Device Reset.
MID Read
Enable
5
5
Figure 7-21. Analog Control
Reserved
Figure 7-22. Channel
REG_ANALOG_CTL
4
REG_CHANNEL
4
Reserved
Channel
3
3
PA Output
Enable
2
2
PA Invert
1
1
CYWUSB6935
Default: 0x00
Default: 0x00
Page 17 of 32
Reset
0
0
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